• Transactions of the Korean Society of Mechanical Engineers A
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• v.39 no.10
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• pp.1011-1019
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• 2015

Insulated-gate bipolar transistors (IGBTs) are the predominantly used power semiconductors for high-current applications, and are used in trains, airplanes, electrical, and hybrid vehicles. IGBT power modules generate a considerable amount of heat from the dissipation of electric power. This heat generation causes several reliability problems and deteriorates the performances of the IGBT devices. Therefore, thermal management is critical for IGBT modules. In particular, realizing a proper thermal design for which the device temperature does not exceed a specified limit has been a key factor in developing IGBT modules. In this study, we investigate the thermal behavior of the 1200 A, 3.3 kV IGBT module package using finite-element numerical simulation. In order to minimize the temperature of IGBT devices, we analyze the effects of various packaging materials and different thickness values on the thermal characteristics of IGBT modules, and we also perform a design-of-experiment (DOE) optimization

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.35 no.6
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• pp.556-561
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• 2022

Computational material science as an application of Density Functional Theory (DFT) to the discipline of material science has emerged and applied to the research and development of energy materials and electronic materials such as semiconductor. However, there are a few difficulties, such as generating input files for various types of materials in both the same calculating condition and appropriate parameters, which is essential in comparing results of DFT calculation in the right way. In this tutorial status report, we will introduce how to create crystal structures and to prepare input files automatically for the Vienna Ab initio Simulation Package (VASP) and Gaussian, the most popular DFT calculation programs. We anticipate this tutorial makes DFT calculation easier for the ones who are not experts on DFT programs.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.17 no.6
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• pp.708-714
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• 2016

In today's semiconductor industry, manufacturing technology is being developed for the purpose of processing large amounts of data and improving the speed of data processing. The packaging process in semiconductor manufacturing is utilized for the purpose of protecting the chips from the external environment and supplying electric power between the terminals. Nowadays, the WLP (Wafer-Level Packaging) process is mainly used in semiconductor manufacturing because of its high productivity. All of the silicon dies on the wafer are subjected to a high pressure and temperature during the molding process, so that die shift and warpage inevitably occur. This phenomenon deteriorates the positioning accuracy in the subsequent re-distribution layer (RDL) process. In this study, in order to minimize the die shift, a vision inspection system is developed to collect the die shift measurement data.

• Journal of the Institute of Convergence Signal Processing
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• v.10 no.2
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• pp.120-126
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• 2009

There are many different types of surface defects on semiconductor Integrated Chips (IC's) caused by various factors during manufacturing process, such as cracks, foreign materials, chip-outs, chips, and voids. These defects must be detected and classified by an inspection system for productivity improvement and effective process control. Among defects, in particular, foreign materials and chips are the most difficult ones to classify accurately. A vision system composed of a carefully designed optical system and a processing algorithm is proposed to detect and classify the defects on QFN(Quad Flat No-leads) packages. The processing algorithm uses features derived from the defect's position and brightness value in the Maximum Likelihood classifier and the optical system is designed to effectively extract the features used in the classifier. In experiments we confirm that this method gives more effective result in classifying foreign materials and chips.

• Journal of Technology Innovation
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• v.28 no.4
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• pp.63-93
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• 2020

We suggest a new way of specifying the co-evolution of product and process technologies, and integrating it into one of the well-received technology intelligence tools - a technology radar. Cross impact analysis enables us to identify the core technologies of product-process co-evolution. Combining expert judgment with its results, we can clarify the technological co-evolution trajectory with mainstream as well as emerging core technologies. Reflecting these in the assessment process of a technology radar, we could improve reliance of the technology assessment process and technology portfolio. From the academic perspective, our research provides a point where the co-evolution theory encouners technology intelligence methods. Practically, strategic capability of future-preparedness and strategic management could improve by adopting our method based on our example of co-evolution of semiconductor product and process technologies.

• Journal of the Microelectronics and Packaging Society
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• v.30 no.4
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• pp.8-16
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• 2023

The importance of next-generation packaging technologies is being emphasized as a solution as the miniaturization of devices reaches its limits. To address the bottleneck issue, there is an increasing need for 2.5D and 3D interconnect pitches. This aims to minimize signal delays while meeting requirements such as small size, low power consumption, and a high number of I/Os. Hybrid bonding technology is gaining attention as an alternative to conventional solder bumps due to their limitations such as miniaturization constraints and reliability issues in high-temperature processes. Recently, there has been active research conducted on SiCN to address and enhance the limitations of the Cu/SiO₂ structure. This paper introduces the advantages of Cu/SiCN over the Cu/SiO₂ structure, taking into account various deposition conditions including precursor, deposition temperature, and substrate temperature. Additionally, it provides insights into the core mechanisms of SiCN, such as the role of Dangling bonds and OH groups, and the effects of plasma surface treatment, which explain the differences from SiO₂. Through this discussion, we aim to ultimately present the achievable advantages of applying the Cu/SiCN hybrid bonding structure.

• Journal of the Microelectronics and Packaging Society
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• v.31 no.3
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• pp.1-9
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• 2024

This paper addresses the significance of Cu/Polymer Hybrid Bonding technology in the advancement of semiconductor packaging. As the demands of the AI era increase, the semiconductor industry is exploring heterogeneous integration packaging technologies to achieve high I/O counts, low power consumption, efficient heat dissipation, multifunctionality, and miniaturization. The conventional Cu/SiO₂ Hybrid Bonding structure faces limitations such as achieving compatibility with CMP processes to attain surface roughness below 1nm and the occurrence of bonding defects due to particles. However, Cu/Polymer Hybrid Bonding technology, utilizing polymers, is gaining attention as a promising alternative to overcome these challenges. This study focuses on the deposition, patterning, and material properties of polymers essential for Cu/Polymer Hybrid Bonding, highlighting the advantages and potential applications of this technology compared to existing methods. Specifically, the use of polymers with low glass transition temperatures (Tg) is discussed for their benefits in low-temperature bonding processes and improved mechanical properties due to their high coefficients of thermal expansion. Furthermore, the study explores surface property modifications of polymers and the enhancement of bonding mechanisms through plasma treatment. This research emphasizes that Cu/Polymer Hybrid Bonding technology can serve as a critical breakthrough in developing high-performance, low-power semiconductor devices within the industry.

• Proceedings of the Korean Institute of Surface Engineering Conference
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• 2016.11a
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• pp.165.2-165.2
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• 2016

현재, 솔더범프용 주석계 도금액의 필수성분인 산화방지제의 경우, 국내외 경쟁사에서는 가격 및 성능이 우수한 벤젠/페놀 계열을 적용 중이다. 그러나, 최근 대형 고객사에서 페놀류 산화방지지제를 환경규제물질로 규정함에 따라, 자사에서는, 특허 이슈 해소 가능한 친환경 대체 산화방지제 개발을 해오고 있다. 본 연구에서는, 반도체 패키지용 주석계 도금액의 산화방지제 종류와 농도에 따른 주요 특성 (Particle, 전류 효율, 안정성 (변색, 침전 외), 범프 두께의 편차, 감광제의 침해, Reflow 후 빈공간 등)에 대하여 살펴보았다.

• Proceedings of the KIPE Conference
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• 2017.11a
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• pp.39-40
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• 2017

본 논문에서는 자성체 및 비자성체 용기 가열이 모두 가능한 Induction Cooker 스위칭 소자를 선정한다. 비자성체 용기 가열 시 스위칭 소자에서 발생하는 손실, 열 저항 및 방열판의 온도를 통해 Package Type에 따른 접합 온도를 계산하여 스위칭 소자를 선정하고 실험을 통해 선정한 스위치의 적합성을 검증한다.

• Proceedings of the KAIS Fall Conference
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• 2009.12a
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• pp.850-853
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• 2009

반도체 조립공정에서 사용되는 Pick and Placement장비는 반도체패키지를 컴퓨터 비젼을 이용하여 위치 정렬하고 Placement Tray에 적재하는 장비로서 고속,고정밀도가 요구된다. 다변량 통계적 분석방법인 주성분 분석법은 주어진 데이터에서 특징이 되는 일정한 패턴을 찾는 방법으로 영상의 차원감소를 위해 최근 많이 사용되어지고 있다. 본 논문에서는 반도체패키지의 기하학적 형태를 이용하여 위치정렬을 하도록 한 후 성능을 검증하도록 하였다. 패키지 원영상에서 밝기값의 차이에 따른 윤곽선을 인식한 후, 각 위치값들을 주성분 분석법을 이용해 직선을 추출한 방법으로 위치정렬한 결과 신뢰할만한 위치정렬 성능을 보였다.