• Tribology and Lubricants
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• 제21권2호
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• pp.71-76
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• 2005

This paper compares of mechanical tensile properties of 6 kinds of copper foil. The beam lead made with copper foil. Different from other package type such as plastic package, Chip Size Package has a reliability problem in beam lead rather than solder joint in board level. A new tensile loading system was developed using voice-coil actuator. The new tensile loading system has a load cell with maximum capacity of 20 N and a non-contact position measuring system based on the principle of capacitance micrometry with 0.1nm resolution for displacement measurement. Strain was calculated from the measured displacement using FE analysis. The comparison of mechanical properties helps designer of package to choose copper for ensuring reliability of beam lead in early stage of semiconductor development.

• E2M - 전기 전자와 첨단 소재
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• 제10권6호
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• pp.519-527
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• 1997

The micro crack was occurred where the stress concentrated by the thermal stress which was induced during the cooling period after molding process or by the various reliability tests. In order to estimate the possibility of development from inside micro crack to outside fracture, the fracture toughness of EMC should be measured under the various applicable condition. But study was conducted very rarely for the above area. In order to provide a was to decide the fracture resistance of EMC (Epoxy Molding Compound) of plastic package which is produced by using transfer molding method, measuring fracture is studied. The specimens were made with various EMC material. The diverse combination of test conditions, such as different temperature, temperature /humidity conditions, different filler shapes, and post cure treatment, were tried to examine the effects of environmental condition on the fracture toughness. This study proposed a way which could improve the reliability of LOC(Lead On Chip) type package by comparing the measured $J_{IC}$ of EMC and the calculated J-integral value from FEM(Finite Element Method). The measured $K_{IC}$ value of EMC above glass transition temperature dropped sharply as the temperature increased. The $K_{IC}$ was observed to be higher before the post cure treatment than after the post cure treatment. The change of $J_{IC}$ was significant by time change. J-integral was calculated to have maximum value the angle of the direction of fracture at the lead tip was 0 degree in SOJ package and -30 degree in TSOP package. The results FEM simulation were well agreed with the results of measurement within 5% tolerance. The package crack was proved to be affected more by the structure than by the composing material of package. The structure and the composing material are the variables to reduce the package crack.ack.

• 한국전기전자재료학회논문지
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• 제31권7호
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• pp.450-454
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• 2018

Because of the rapidly changing environment and high uncertainties, the semiconductor industry is in need of appropriate forecasting technology. In particular, both the cost and time in the test process are increasing because the process becomes complicated and there are more factors to consider. In this paper, we propose a prediction model that predicts a final "good" or "bad" on the basis of preconditioning test data generated in the semiconductor test process. The proposed prediction model solves the classification and regression problems that are often dealt with in the semiconductor process and constructs a reliable prediction model. We also implemented a prediction model through various machine learning algorithms. We compared the performance of the prediction models constructed through each algorithm. Actual data of the semiconductor test process was used for accurate prediction model construction and effective test verification.

• JSTS:Journal of Semiconductor Technology and Science
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• 제4권3호
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• pp.182-188
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• 2004

We demonstrate a $2.1\;{\times}\;1.0\;{\times}\;0.1cm^3$ sized compact transmitter using LTCC System-in-Package (SiP) technology for 60GHz-band wireless communication applications. For low-attenuation characteristics and resonance suppression of the SiP, we have proposed and demonstrated a coplanar double wire-bond transition and novel CPW-to-stripline transition integrating air-cavities as well as novel air-cavities embedded CPW line. The fabricated transmitter achieves an output of 13dBm at a RF frequency of 62GHz, an IF frequency of 2.4GHz, and a LO frequency of 59.6GHz. The up-conversion gain is 11dB, while the LO signal is suppressed with the image rejection mixer below -21.4dBc, and the image and spurious signals are also suppressed below -31dBc.

• 한국마이크로전자및패키징학회:학술대회논문집
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• 한국마이크로전자및패키징학회 2003년도 International Symposium
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• pp.165-172
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• 2003

Wafer-level packaging technology has become established with increase of demands for miniaturizing and realizing lightweight electronic devices evolution. This packaging technology enables the smallest footprint of packaged chip. Various structures and processes has been proposed and manufactured currently, and products taking advantages of wafer-level package come onto the market. The package enables mounting semiconductor chip on print circuit board as is a case with conventional die-level CSP's with BGA solder bumps. Bumping technology is also advancing in both lead-free solder alternative and wafer-level processing such as stencil printing using solder paste. It is known lead-free solder bump formation by stencil printing process tend to form voids in the re-flowed bump. From the result of FEM analysis, it has been found that the strain in solder joints with voids are not always larger than those of without voids. In this paper, characteristics of wafer-level package and effect of void in solder bump on its reliability will be discussed.

• JSTS:Journal of Semiconductor Technology and Science
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• 제12권3호
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• pp.320-330
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• 2012

In this paper, we investigate the power integrity of grid structures for power and ground distribution on printed circuit board (PCB). We propose the 2D transmission line method (TLM)-based model for efficient frequency-dependent impedance characterization and PCB-package-integrated circuit (IC) co-simulation. The model includes an equivalent circuit model of fringing capacitance and probing ports. The accuracy of the proposed grid model is verified with test structure measurements and 3D electromagnetic (EM) simulations. If the grid structures replace the plane structures in PCBs, they should provide effective shielding of the electromagnetic interference in mobile systems. An analytical model to predict the shielding effectiveness (SE) of the grid structures is proposed and verified with EM simulations.

• 대한산업공학회지
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• 제41권4호
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• pp.408-413
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• 2015

The quality prediction of the semiconductor industry has been widely recognized as important and critical for quality improvement and productivity enhancement. The main objective of this paper is to predict the final quality of semiconductor chips based on fail bit count information obtained from probe tests. Our proposed method consists of solving the data imbalance problem, non-parametric variable selection, and adjusting the parameters of the model. We demonstrate the usefulness and applicability of the proposed procedure using a real data from a semiconductor manufacturing.

• Journal of Power Electronics
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• 제9권3호
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• pp.464-471
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• 2009

This paper introduces a new Motion-$SPM^{TM}$ (Smart Power Modules) module in Single In-line Package (SIP), which is a fully optimized intelligent integrated IGBT inverter module for up to 1kW low power motor drive applications. This module offers a sophisticated, integrated solution and tremendous design flexibility. It also takes advantage of pliability for the arrangement of heat-sink due to two types of lead forms. It comes to be realized by employing non-punch-through (NPT) IGBT with a fast recovery diode and highly integrated building block, which features built-in HVICs and a gate driver that offers more simplicity and compactness leading to reduced costs and high reliability of the entire system. This module also provides technical advantages such as the optimized cost effective thermal performances through IMS (Insulated Metal Substrate), the high latch immunity. This paper provides an overall description of the Motion-$SPM^{TM}$ in SIP as well as actual application issues such as electrical characteristics, thermal performance, circuit configurations and power ratings.

• 한국마이크로전자및패키징학회:학술대회논문집
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• 한국마이크로전자및패키징학회 2003년도 기술심포지움 논문집
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• pp.53-58
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• 2003

The Wafer Level Packaging is one of the most important technologies in the semiconductor industry today. Its primary advantages are its small form factor and low cost potential for manufacturing including test procedure. The CASIO's WLP samples, application example and the structure are shown in Fig.1, 2&3. There are dielectric layer , under bump metal, re-distribution layer, copper post , encapsulation material and terminal solder .The key technologies are 'Electroplating thick copper process' and 'Unique wafer encapsulation process'. These are very effective in getting electrical and mechanical advantages of package. (Fig. 4). CASIO and CMK are developing a new System Packaging technology called the Embedded Wafer Level Package (EWLP) together. The active components (semiconductor chip) in the WLP structure are embedded into the Printed Wiring Board during their manufacturing process. This new technical approach has many advantages that can respond to requirements for future mobile products. The unique feature of this EWLP technology is that it doesn't contain any solder interconnection inside. In addition to improved electrical performance, EWLP can enable the improvement of module reliability. (Fig.5) The CASIO's WLP Technology will become the effective solution of 'KGD problem in System Packaging'. (Fig. 6) The EWLP sample shown in Fig.7 including three chips in the WLP form has almost same structure wi_th SoC's. Also, this module technology are suitable for RF and Analog system applications. (Fig. 8)

• 반도체디스플레이기술학회지
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• 제16권1호
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• pp.16-21
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• 2017

In this paper, the effect of battery-package shape of electric vehicle on the forced convection around a group of battery cells has been numerically investigated. Simulations for the two package shapes with straight/curved ducts have been conducted to examine the two design factors; the maximum temperature and the temperature deviation of a group of cells which influence the cell durability. The simulation of the conjugate heat transfer has been simplified by employing an equivalent thermal conductivity of cell that consists of various materials. It has been found that the maximum temperature and the temperature deviation of curved duct were lower than those of straight duct. Velocity fields have also been examined to describe the temperature distribution of a group of cells and the position of maximum temperature was found to be related to the dead zone of flow field.