• Journal of Electrical Engineering and Technology
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• v.2 no.1
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• pp.89-97
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• 2007

This paper presents a new circuit topology of active edge resonant snubbers assisted half-bridge soft switching PWM inverter type DC-DC high power converter for DC bus feeding power plants. The proposed DC-DC power converter is composed of a typical voltage source-fed half-bridge high frequency PWM inverter with a high frequency planar transformer link in addition to input DC busline side power semiconductor switching devices for PWM control scheme and parallel capacitive lossless snubbers. The operating principle of the new DC-DC converter treated here is described by using switching mode equivalent circuits, together with its unique features. All the active power switches in the half-bridge arms and input DC buslines can achieve ZCS turn-on and ZVS turn-off commutation transitions. The total turn-off switching losses of the power switches can be significantly reduced. As a result, a high switching frequency IGBTs can be actually selected in the frequency range of 60 kHz under the principle of soft switching. The performance evaluations of the experimental setup are illustrated practically. The effectiveness of this new converter topology is proved for such low voltage and large current DC-DC power supplies as DC bus feeding from a practical point of view.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.11 no.2
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• pp.189-194
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• 2018

Nowadays most integrated circuits are built using the bulk CMOS technology, but it has much difficulty in further reduction of the power consumption and die size. As a super low-power technology to solve such problems, the SOI technology attracts great attention recently. In this paper, the study results of the temperature dependency of the hot carrier effects in the n-channel MOSFETs fabricated on the thin SOI substrate were discussed. In spite that the devices employed the LDD structure, the hot carrier effects were more serious than expected due to the high series resistance between the channel region and the substrate contact to the ground, and were found to be less serious for the higher temperature with the more phonon scattering in the channel region, which resulted in reducing the hot electron generation.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.13 no.4
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• pp.87-95
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• 1999

A primary limitation of the awlication of New class of solid state high power, high speed electronic device, narrely, the Photo-Conductive Power Switch(PCPS) is that the switches flashover at the surlace under average awlied fields much less than the bulk breakdown field of the semiconductor in most cases. The only way overcome those problffi1 and has a workable compact solid state switch is to passivate the surlace by a solid state dielectric material. In this experirrentation, The voltage withstands of Silicon is to be severely degraded when operated in vacuum(10[kV/cm]) and the perlormance is improved when operated in air(30[kV/cm[), in SF6(80~100[kV/cm]). After the passivation, the device had a breakdown field in vacuum and air at a field as high as the unpassivated device in SF6. A experirrent results show passivated devices have excellent breakdown field. In this paper, We improved the main properties and mechanism of the silicon breakdown before and after passivation under high field. field.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• v.9 no.2
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• pp.865-868
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• 2005

We fabricated the $Pb_{0.72}La_{0.28}TiO_3 (PLT(28))$ thin film successfully by using the sol-gel method and characterized it to evaluate its potential for being utilized as the capacitor dielectrics of ULSI DRAMs. In our sol-gel process, the acetates were used as the starting materials. Through the TGA-DTA analysis, we established the excellent fabrication conditions of the sol-gel method for the PLT(28) thin film. We obtained the dense and crack-free PLT(28) thin film of 100% perovskite phase by drying at 350$^{\circ}C$ after each coating and final annealing at 650$^{\circ}C$. Electrical properties of PLT(28) thin film were measured through formation on the Pt/Ti/SiO$_2$/Si substrate and its dielectric constant and leakage current density were measured as 936 and 1.1${\mu}$A/cm$^2$, respectively

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.24 no.9
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• pp.701-709
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• 2011

In semiconductor wafer fabrication, etching is one of the most critical processes, by which a material layer is selectively removed. Because of difficulty to correct a mistake caused by over etching, it is critical that etch should be performed correctly. This paper proposes a new approach for etch endpoint detection of small open area wafers. The traditional endpoint detection technique uses a few manually selected wavelengths, which are adequate for large open areas. As the integrated circuit devices continue to shrink in geometry and increase in device density, detecting the endpoint for small open areas presents a serious challenge to process engineers. In this work, a high-resolution optical emission spectroscopy (OES) sensor is used to provide the necessary sensitivity for detecting subtle endpoint signal. Partial Least Squares (PLS) method is used to analyze the OES data which reduces dimension of the data and increases gap between classes. Support Vector Machine (SVM) is employed to detect endpoint using the data after PLS. SVM classifies normal etching state and after endpoint state. Two data sets from OES are used in training PLS and SVM. The other data sets are used to test the performance of the model. The results show that the trained PLS and SVM hybrid algorithm model detects endpoint accurately.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.30 no.8
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• pp.525-529
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• 2017

Molybdenum oxide ($MoO_3$) offers pivotal advantages for high optical transparency and low light reflection. Considering device fabrication, n-type $MoO_3$ semiconductor can spontaneously establish a junction with p-type Si. Since the energy bandgap of Si is 1.12 eV, a maximum photon wavelength of around 1,100 nm is required to initiate effective photoelectric reaction. However, the utilization of infrared photons is very limited for Si photonics. Hence, to enhance the Si photoelectric devices, we applied the wide energy bandgap $MoO_3$ (3.7 eV) top-layer onto Si. Using a large-scale production method, a wafer-scale $MoO_3$ device was fabricated with a highly crystalline structure. The $MoO_3/p-Si$ heterojunction device provides distinct photoresponses for long wavelength photons at 900 nm and 1,100 nm with extremely fast response times: rise time of 65.69 ms and fall time of 71.82 ms. We demonstrate the high-performing $MoO_3/p-Si$ infrared photodetector and provide a design scheme for the extension of Si for the utilization of long-wavelength light.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.66 no.12
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• pp.1889-1894
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• 2017

Global automobile manufacturers are developing electric vehicles (EVs) to eliminate the pollutant emissions from internal combustion vehicles and to minimize fossil fuel consumptions for the future generations. However, EVs have a disadvantage of shorter traveling distance than that of conventional vehicles. To answer this shortfall, more batteries are installed in the EV to satisfy the consumer expectation for the driving range. However, as the energy capacity of the battery mounted in the EV increases, the amount of heat generated by each cell also increases. Naturally, a better battery thermal management system (BTMS) is required to control the temperature of the cells efficiently because the appropriate thermal environment of the cells greatly affects the power output from the battery pack. Typically, the BTMS is divided into an active and a passive system depending on the energy usage of the thermal management system. Heat exchange materials usually include gas and liquid, semiconductor devices and phase change material (PCM). In this study, an application of PCM for a BTMS was investigated to maintain an optimal battery operating temperature range by utilizing characteristics of a PCM, which can accumulate large amounts of latent heat. The system was modeled using Dymola from Dassault Systems, a multi-physics simulation tool. In order to compare the relative performance, the BTMS with the PCM and without the PCM were modeled and the same battery charge/discharge scenarios were simulated. Number of analysis were conducted to compare the battery cooling performance between the model with the aluminum case and PCM and the model with the aluminum case only.

• Proceedings of the Korean Institute of IIIuminating and Electrical Installation Engineers Conference
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• 2006.05a
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• pp.399-402
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• 2006

This paper presents a new circuit topology of dc bus line switch-assisted half-bridge soft switching PWM inverter type dc-dc converter for arc welder. The proposed power converter is composed of typical voltage source half-bridge high frequency PWM inverter with a high frequency transformer link in addition to dc bus line side power semiconductor switching devices fer PWM control scheme and capacitive lossless snubbers. All the active power switches in the half-bridge arm and dc bus lines can achieve ZCS turn-on and ZVS turn-off commutation operation and consequently the total turn-off switching losses can be significantly reduced. As a result, a high switching frequency of using IGBTs can be actually selected more than about 20 kHz. The effectiveness of this new converter topology is proved for low voltage and large current dc-dc power supplies such as arc welder from a practical point of view.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2007.11a
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• pp.523-524
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• 2007

This paper discusses the planarization process of thick copper film structure used for power supply device. Chemical mechanical polishing(CMP) has been used to remove a metal film and obtain a surface planarization which is essential for the semiconductor devices. For the thick metal removal, however, the long process time and other problems such as dishing, delamination and metal layer peeling are being issued, Compared to the traditional CMP process, Electro-chemical mechanical planarization(ECMP) is suggested to solve these problems. The two-step process composed of the ECMP and the conventional CMP is used for this experiment. The first step is the removal of several tens ${\mu}m$ of bulk copper on patterned wafer with ECMP process. The second step is the removal of residual copper layer aimed at a surface planarization. For more objective comparison, the traditional CMP was also performed. As an experimental result, total process time and process defects are extremely reduced by the two-step process.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2007.11a
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• pp.96-96
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• 2007

Low voltage organic TFTs (OTFTs) and ZnO based TFTs (<5V), utilizing room temperature deposited $Bi_{1.5}Zn_{1.0}Nb_{1.5}O_7$ (BZN) thin films were recently reported, pointing to high-k gate insulators as a promising route for realizing low voltage operating flexible electronics. $Bi_{1.5}Zn_{1.0}Nb_{1.5}O_7$ (BZN) thin film is one of the most promising materials for gate insulator because of its large dielectric constant (~60) at room temperature. However their tendency to suffer from relatively high leakage current at low electric field (>0.3MV/cm) hinder the application of BZN thin films for gate insulator. In order to improve leakage current characteristics of BZN thin film, we mixed 30mol% MgO with 70mol% BZN and their dielectric and electric properties were characterized. We fabricated field-effect transistors with transparent oxide semiconductor ZnO serving as the electron channel and high-k $(Bi_{1.5}Zn_{1.0}Nb_{1.5}O_7)_{0.7}(MgO)_{0.3}$ as the gate insulator. The devices exhibited low operation voltages (<4V) due to high capacitance of the $(Bi_{1.5}Zn_{1.0}Nb_{1.5}O_7)_{0.7}(MgO)_{0.3}$ dielectric.