• 한국진공학회:학술대회논문집
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• 한국진공학회 2014년도 제46회 동계 정기학술대회 초록집
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• pp.346.2-346.2
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• 2014

To use the GaN based light-emitting diodes (LEDs) as solid state lighting sources, the improvement of light extraction and internal quantum efficiency is essential factors for high brightness LEDs. In this study, we suggested the new materials system of a zinc tin oxide (ZTO) layer formed on blue LED epi-structures to improve the light extraction. ZTO is a representative n-type oxide material consisted of ZnO and SnO system. Moreover, ZTO is one of the promising oxide semiconductor material. Even though ZTO has higher chemical stability than IGZO owing to its SnO2 content this has high mobility and high reliability. After formation of ZTO layer on p-GaN layer by using the spin coating method, structural and optical properties are investigated. The x-ray diffraction (XRD) measurement results show the successful formation of ZTO. The photoluminescence (PL) and absorption spectrum shows that it has 3.6-4.1eV band gap. Finally, the light extraction properties of ZTO/LED chip using electroluminescence (EL) measurement were investigated. The experimental and theoretical analyses were simultaneously conducted.

• KIEE International Transactions on Electrophysics and Applications
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• 제5C권1호
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• pp.14-17
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• 2005

In this paper, an automated methodology for generating model parameters considering real manufacturing processes is presented with verified results. In addition, the outcomes of applications to the next generation of flash memory devices using the parameters calibrated from the process specification decision are analyzed. The test vehicle is replaced with a well-calibrated TCAD simulation. First, the calibration methodology is introduced and tested for a flash memory device. The calibration errors are less than 5% of a full chip operation, which is acceptable to designers. The results of the calibration are then used to predict the I-V curves and the model parameters of various transistors for the design of flash devices.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 2000년도 제15차 학술회의논문집
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• pp.467-467
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• 2000

In this paper, a structural design method of robust motion controllers for high-accuracy positioning systems, which makes it possible to predict the performance of the whole closed-loop system, is proposed. First, a stabilizing control input is designed based on robust internal-loop compensate.(RTC) for the system in the presence of uncertainty and disturbance. Next, using the structural characteristics of the RIC, disturbance attenuation properties and the performance of the closed-loop system determined by the variation of controller gains are analyzed. Through this analysis, in some specific applications, it is shown that if the control gain of RIC is increased by N times, the magnitude of error is reduced to its 1/N. Finally, the proposed method is verified through experiments using a high-accuracy positioning system used in the semiconductor chip mounting devices.

• 한국정밀공학회지
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• 제16권5호통권98호
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• pp.40-47
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• 1999

In CMP for semiconductor wafer films, the acceptable within-chip planarity, within-wafer and wafer-to-wafer nonuniformity could be achieved by conditioning. The role of conditioning is to remove continuously polishing residues from pad and to maintain the initial pad surface pores. To reach these requirements, the diamond grits disk has been considered as a conventional conditioner. However, we have investigated many defects as scratch on wafers out of diamond grits shedding, contaminations from bonding materials, and pad pore subsidences by over-conditioning. So, this paper studies the effect of ultrasonic vibration in CMP conditioning as a representative. The effect of ultrasonic vibration was certified through ILD, Metal CMP.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2012년도 제42회 동계 정기 학술대회 초록집
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• pp.531-531
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• 2012

So many groups have been researching the green quantum dots such as InP, InP/ZnS for overcoming the semiconductor nanoparticles composed with heavy metals like as Cd and Pb so on. In spite of much effort to keep up CdSe quantum dots, it does not reach the good properties compared with CdSe/ZnS quantum dots. This quantum dot has improved its properties through the generation of core/shell CdSe/ZnS structure or core/multi-shell structures like as CdSe/CdS/ZnS and CdSe/CdS/ CdZnS/ZnS. In this research, we try to synthesize the InP multi-shell structure by the successiveion layer absorption reaction (SILAR) in the one pot. The synthesized multi-shell structure has improved quantum yield and photo-stability. To generate white light, highly luminescent InP multi-shell quantum dots were mixed with yellow phosphor and integrated on the blue LED chip. This InP multi-shell improved red region of the LEDs and generated high CRI.

• 한국전기전자재료학회논문지
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• 제15권12호
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• pp.1021-1026
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• 2002

As the development of semiconductor process technology continue to advance, ICs continue their trend toward higher performance low power system-on-chip (SOC). These circuits require on board multi power supply. In this paper, a 0.5 ㎛ dual date oxide CMOS Process technology for multi-power application is demonstrated. 5 V and 20 V devices fabricated by proposed process is measured. From 5 V devices using dual gate precess, we got almost the same characteristics as are obtained from standard 5 V devices. And the characteristics of the 20 V device demonstrates that 3 ㎛ devices with minimum gate length are available without reliability degradation. Electrical parameters in minimum 3 ㎛ devices are 520 ㎂/㎛ current density, 120 ㎷ DIBL, 24 V BV for NMOS and ,350 ㎂/㎛ current density, 180 ㎷ DIBL, 26 V BV for PMOS, respectively.

• JSTS:Journal of Semiconductor Technology and Science
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• 제2권1호
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• pp.19-29
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• 2002

A simple and analytical design approach for input power matched CMOS RF LNA circuits and their scaling for lower power consumption, is introduced. In spite of the simplicity of our expressions, it gives excellent agreement with numerical simulation results using commercial CAD tools for several circuit examples performed at 2.4GHz using $0.18\mu\textrm{m}$ CMOS technology. These simple and analytical results are extremely useful in that they can provide enough insights not only for designing any CMOS LNA circuits, but also for characterizing and diagnosing them whether being prototyped or manufactured.

• JSTS:Journal of Semiconductor Technology and Science
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• 제7권3호
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• pp.133-139
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• 2007

Future MEMS systems will be composed of larger varieties of devices with very different functionality such as electronics, mechanics, optics and bio-chemistry. Integration technology of heterogeneous devices must be developed. This article first deals with the current development trend of new fabrication technologies; those include self-assembling of parts over a large area, wafer-scale encapsulation by wafer-bonding, nano imprinting, and roll-to-roll printing. In the latter half of the article, the concept towards the heterogeneous integration of devices and functionality into micro/nano systems is described. The key idea is to combine the conventional top-down technologies and the novel bottom-up technologies for building nano systems. A simple example is the carbon nano tube interconnection that is grown in the via-hole of a VLSI chip. In the laboratory level, the position-specific self-assembly of nano parts on a DNA template was demonstrated through hybridization of probe DNA segments attached to the parts. Also, bio molecular motors were incorporated in a micro fluidic system and utilized as a nano actuator for transporting objects in the channel.

• JSTS:Journal of Semiconductor Technology and Science
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• 제16권3호
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• pp.380-386
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• 2016

This paper presents a compact and low-power on-chip touch sensor and readout circuit using shunt proximity touch sensor and its design scheme. In the proposed touch sensor readout circuit, the touch panel condition depending on the proximity of the finger is directly converted into the corresponding voltage level without additional signal conditioning procedures. Furthermore, the additional circuitry including the comparator and the flip-flop does not consume any static current, which leads to a low-power design scheme. A new prototype touch sensor readout integrated circuit was fabricated using complementally metal oxide silicon (CMOS) $0.18{\mu}m$ technology with core area of $0.032mm^2$ and total current of $125{\mu}A$. Our measurement result shows that an actual 10.4 inches capacitive type touch screen panel (TSP) can detect the finger size from 0 to 1.52 mm, sharply.

• JSTS:Journal of Semiconductor Technology and Science
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• 제16권3호
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• pp.352-358
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• 2016

A 5-phase phase-locked loop (PLL) for USB2.0 applications was implemented by using an all-synthesis technique. The length of the time-to-digital converter for the fine phase detector was halved by the operation of a coarse phase detector that uses 5-phase clocks. The maximum time difference between the rising edges of two adjacent-phase clocks was 6 ps at 480 MHz. The PLL chip in a 65-nm process occupies $0.038mm^2$, consumes 4.8 mW at 1.2 V. The measured rms and peak-to-peak output jitters are 8.6 ps and 45 ps, respectively.