• Journal of Space Technology and Applications
• /
• v.3 no.4
• /
• pp.333-341
• /
• 2023

This study aims to develop technology for testing and verifying the space radiation environment of miniature space components using the facilities of the domestic 100 MeV proton accelerator and the Space Component Test Facility at the Space Testing Center. As advancements in space development progress, high-performance satellites increasingly rely on densely integrated circuits, particularly in core components components like memory. The application of semiconductor components in essential devices such as solar panels, optical sensors, and opto-electronics is also on the rise. To apply these technologies in space, it is imperative to undergo space environment testing, with the most critical aspect being the evaluation and testing of space components in high-energy radiation environments. Therefore, the Space Testing Center at the Korea testing laboratory has developed a radiation testing device for memory components and conducted radiation impact assessment tests using it. The investigation was carried out using 100 MeV protons at a low flux level achievable at the Gyeongju Proton Accelerator. Through these tests, single event upsets observed in memory semiconductor components were confirmed.

• Korean Journal of Materials Research
• /
• v.1 no.1
• /
• pp.23-28
• /
• 1991

The resistivity of polycrystalline silicon film deposited by low pressure chemical vapor deposition and doped by arsenic Implantation has been investigated as a function of dopant concentration and testing temperature ranging from $25^{\circ}C$ to $105^{\circ}C$ . The resistivity vs. doping concentration curve had a peak point with highest activation energy with respect to the dependence of the resistivity on temperature. We showed that $O_2$ plasma anneal followed by heat-treatment in $N_2$ ambient was able to recover the resistivity degraded by the plasma deposited passivation layers.

• Journal of the Microelectronics and Packaging Society
• /
• v.21 no.4
• /
• pp.33-39
• /
• 2014

To establish the reliability of a packaging structures, adhesion testing of key interfaces is a critical task. Due to the material mismatch, the interface may be prone to delamination failure due to conditions during the manufacturing of the product or just from the day-to-day use. To assess the reliability of the interface adhesion strength testing can be performed during the design phase of the product. One test method of interest is the four-point bending (4PB) adhesion strength test method. This test method has been implemented in a variety of situations to evaluate the adhesion strength of interfaces in bimaterial structures to the interfaces within thin film multilayer stacks. This article presents a review of the 4PB adhesion strength testing method and key implementations of the technique in regards to semiconductor packaging.

• Journal of Korean Society of Industrial and Systems Engineering
• /
• v.23 no.60
• /
• pp.73-81
• /
• 2000

The testing processes for VLSI finished devices are considerably complex because they require different types of ATE to be linked together. Due to the interaction effect between two or more linked ATEs, it is difficult to trace down the cause of the unexpected longer ATE setup time and random yields, which frequently occur in the VLSI circuit-testing laboratory. The goal of this paper is to develop and demonstrate the methodology designed to eliminate the possible interaction factors that might affect the random yields and/or unexpected longer setup time as well as increase the productivity. The statistical method such as design of experiment or multivariate analysis cannot be applied to the final testing floor here directly due to the environmental constraints. Expanded product data information (PDI) is constructed by combining product data information and ATE control information. An architecture utilizing expanded PDI is designed, which enables the engineer to conduct statistical approach investigation and reduce the setup time, as well as increase yield.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.17 no.1
• /
• pp.147-155
• /
• 2017

A new endurance test-pattern generation on NAND-flash memory is proposed to improve test cost. We mainly focus on the correlation between the data-pattern and the device error-rate during endurance testing. The novelty is the development of testing method using quasi-random pattern based on device architectures in order to increase the test efficiency during time-consuming endurance testing. It has been proven by the experiments using the commercial 32 nm NAND flash-memory. Using the proposed method, the error-rate increases up to 18.6% compared to that of the conventional method which uses pseudo-random pattern. Endurance testing time using the proposed quasi-random pattern is faster than that of using the conventional pseudo-random pattern since it is possible to reach the target error rate quickly using the proposed one. Accordingly, the proposed method provides more low-cost testing solutions compared to the previous pseudo-random testing patterns.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.18 no.5
• /
• pp.431-438
• /
• 2005

In this paper, we propose the built-in current testing circuit for improving reliability As the integrated CMOS circuits in a chip are increased, the testability on design and fabrication should be considered to reduce the cost of testing and to guarantee the reliability In addition, the high degree of integration makes more failures which are different from conventional static failures and introduced by the short between transistor nodes and the bridging fault. The proposed built-in current testing method is useful for detecting not only these failures but also low current level failures and faster than conventional method. In normal mode, the detecting circuit is turned off to eliminate the degradation of CUT(Circuits Under Testing). The differential input stage in detecting circuit prevents the degradation of CUT in test mode. It is expected that this circuit improves the quality of semiconductor products, the reliability and the testability.

• Proceedings of the Korean Society of Precision Engineering Conference
• /
• 2013.05a
• /
• pp.485-486
• /
• 2013

• Journal of the Korean Society of Safety
• /
• v.16 no.2
• /
• pp.57-62
• /
• 2001

In order to analyze the mechanism of semiconductor device damages by ESD, this paper adopts a new charged-device model(CDM), field-induced charged nudel(FCDM), simulator that is suitable for rapid routine testing of semiconductor devices and provides a fast and inexpensive test that faithfully represents ESD hazards in plants. The high voltage applied to the device under test is raised by the fie]d of non-contacting electrodes in the FCDM simulator. which avoids premature device stressing and permits a faster test cycle. Discharge current md time are measured and calculated The FCDM simulator places the device at a huh voltage without transferring charge to it, by using a non-contacting electrode. The only charge transfer in the FCMD simulator happens during the discharge. This paper examine the field charging mechanism, measure device thresholds, and analyze failure modes. The FCDM simulator provides a Int and inexpensive test that faithfully represents factory ESD hazards. The damaged devices obtained in the simulator are analyzed and evaluated by SEM Also the results in this paper can be used for to prevent semiconductor devices from ESD hazards.

• Journal of the Korean Society of Manufacturing Process Engineers
• /
• v.21 no.9
• /
• pp.1-11
• /
• 2022

Recently, there has been continuous technological development in the semiconductor industry, and semiconductor manufacturing technologies are being advanced and highly integrated. For this reason, ceramic material having excellent heat resistance, wear resistance, and conductivity are used as components in semiconductor manufacturing. Among them, the probe card's space transformer is used as ceramic material to prevent electronic signal noise during the electrical die sorting of semiconductor function testing. However, implementing a bulk-type space transformer with a thickness of 5.6 mm or more is challenging, and thus it is produced in a structure with a stacked ceramic film. The stacked space transformer has low productivity because it is difficult to ensure hole clogging and a precise shape. In this research, an ultrasonic horn is designed to manufacture a bulk-type ceramic space transformer through ultrasonic drilling. Vibration characteristics were analyzed according to the ultrasonic horn, and the natural frequency was measured.

• Journal of the Semiconductor & Display Technology
• /
• v.16 no.3
• /
• pp.71-77
• /
• 2017

As the automobile industry has shifted to software, the Automotive SPICE standard has been established to ensure efficient product development process and quality. In the assessment model, the HIS Scope is the minimum standard for small and medium automotive electric companies to meet OEM requirements. However, in order to achieve the HIS Scope, the output of each process stage that meets the verification criteria of Automotive SPICE must be created. In particular, the test phase takes a lot of resources, which is a big burden for small and medium-sized companies. In this paper, we propose a methodology for creating test cases of software integration test phase based on UML sequence diagram, which is a software design phase of Automotive SPICE HIS Scope, by applying behavior model based testing method. We also propose a tool chain for automating the creation process. This will reduce the resources required to create a test case.