• Journal of the Korean Institute of Telematics and Electronics D
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• v.35D no.6
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• pp.37-45
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• 1998

In this paper, we report the first three-dimensional simulation result of the transient enhanced diffusion(TED) of dopants in the ion-implanted silicon by employing our 3D semiconductor process simulator, INPROS system. In order to simulate three-dimensional TED redistribution of dopants in silicon, the dopant distributions after the ion implantation was calculated by Monte Carlo(MC) method, followed by finite element(FE) numerical solver for thermal annealing. Excellent agreement between the simulated 3D profile and the SIMS data has been obtained for ion-implanted arsenic and phosphorus after annealing the boron marker layer at 75$0^{\circ}C$ for 2 hours. Our three-dimensional TED simulation could successfully explain the reverse short channel effect(RSCE) by taking the 3D point defect distribution into account. A coupled TED simulation and device simulation allows reverse short channel effect on threshold to be accurately predicted.

• Transactions of the Korean Society of Mechanical Engineers B
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• v.30 no.4 s.247
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• pp.306-313
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• 2006

Automated material handling system is being used as a method to reduce manufacturing cost in the semiconductor and flat panel displays (FPDs) manufacturing process. Those are considering switch-over from the traditional cassette system to single-substrate transfer system to reduce raw materials of stocks in the processing line. In the present study, the wafer transportation speed has been evaluated by numerical and experimental method for three propulsion nozzle array (face, front, rear) in an air levitation system. Test facility for 300 mm wafer was equipped with two control tracks and a transfer track of 1,500mm length. The diameter of propulsion nozzle is 0.8mm and air velocity of wafer propulsion is $50\sim150m/s$. We found that the experimental results of the wafer transportation speed were well agreed with the numerical ones. Namely, the predicted values of the maximum wafer transportation speed are higher than those values of experimental data by 16% and the numerical result of the mean wafer transportation speed is higher than the experimental result within 20%.

• Journal of the Korean Society for Precision Engineering
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• v.33 no.11
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• pp.893-898
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• 2016

Plastic array lens are cheap to manufacture; however, plastic is not resistant to high temperatures and moisture. Optical glass represents a better solution but is a more-expensive alternative. Glass array lens can be produced using lithography or precision-molding techniques. The lithography process is commonly used, for instance, in the semiconductor industry; however, the manufacturing costs are high, the processing time is quite long, and spherical aberration is a problem. To obtain high-order aspherical shapes, mold-core manufacturing is conducted through ultra-precision grinding machining. In this paper, a $4{\times}1$ mold core was manufactured using an ultra-precision machine with a jig for the injection molding of an aspherical array lens. The machined mold core was measured using the Form TalySurf PGI 2+ contact-stylus profilometer. The measurement data of the mold core are suitable for the design criterion of below 0.5 um.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.3
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• pp.300-311
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• 2016

The analog-to-digital-converter-based (ADC-based) backplane receivers that consist of a front-end ADC followed by a digital equalizer are gaining more popularity in recent years, as they support more sophisticated equalization required for high data rates, scale better with fabrication technology, and are more immune to PVT variations. Unfortunately, designing an ADC-based receiver that meets tight power and performance budgets of high-speed backplane link systems is non-trivial as both front-end ADC and digital equalizer can be power consuming and complex when running at high speed. This paper reviews the state of art designs for the front-end ADC and digital equalizers to suggest implementation choices that can achieve high speed while maintaining low power consumption and complexity. Design-space exploration using system-level models of the ADC-based receiver allows through analysis on the impact of design parameters, providing useful information in optimizing the power and performance of the receiver at the early stage of design. The system-level simulation results with newer device parameters reveal that, although the power consumption of the ADC-based receiver may not comparable to the receivers with analog equalizers yet, they will become more attractive as the fabrication technology continues to scale as power consumption of digital equalizer scales well with process.

• ETRI Journal
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• v.35 no.4
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• pp.594-602
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• 2013

This paper proposes printed organic one-time programmable read-only memory (PROM). The organic PROM cell consists of a capacitor and an organic p-type metal-oxide semiconductor (PMOS) transistor. Initially, all organic PROM cells with unbroken capacitors store "0." Some organic PROM cells are programmed to "1" by electrically breaking each capacitor with a high voltage. After the capacitor breaking, the current flowing through the PROM cell significantly increases. The memory data is read out by sensing the current in the PROM cell. 16-bit organic PROM cell arrays are fabricated with the printed organic PMOS transistor and capacitor process. The organic PROM cells are programmed with -50 V, and they are read out with -20 V. The area of the 16-bit organic PROM array is 70.6 $mm^2$.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.1
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• pp.48-52
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• 2014

In this paper, scaling down characteristics of vertical channel phase random access memory are investigated with device simulator and finite element analysis simulator. Electrical properties of select transistor are obtained by device simulator and those of phase change material are obtained by finite element analysis simulator. From the fusion of both data, scaling properties of vertical channel phase change random access memory (VPCRAM) are considered with ITRS roadmap. Simulation of set reset current are carried out to analyze the feasibility of scaling down and compared with values in ITRS roadmap. Simulation results show that width and length ratio of the phase change material (PCM) is key parameter of scaling down in VPCRAM. Thermal simulation results provide the design guideline of VPCRAM. Optimization of phase change material in VPCRAM can be achieved by oxide sidewall process optimization.

• Journal of ILASS-Korea
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• v.24 no.1
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• pp.8-14
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• 2019

The purpose of this study is to develop a packing-free wet scrubber to prolong the maintenance interval compared with the conventional packed bed wet scrubbers with which frequent operation stops are unavoidable to clean the packing materials. The main- and interaction-effects were quantitatively analyzed by regression analysis for the measured ammonia scrubbing data from the experiments prepared by experimental design. The scrubbing efficiency of the newly developed wet scrubber was found to be over 95% under the condition of flue gas flow rate of 90CMM and liquid-to-gas ratio $2l/m^3$ for all considered trials of experimental design. The interaction effect between the inlet duct spray and the filter was found to be important, which controls the droplet growth due to the droplet collisions between the duct- and scrubbing tower-spray. The presented methodology to analyze the impacts of operational and design factors on the scrubber efficiency showed potential for applications to optimize the future flue gas abatement process in semiconductor plants.

• Mass Spectrometry Letters
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• v.12 no.2
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• pp.47-52
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• 2021

Evaluating the impurity concentrations in semiconductor thin films using time of flight secondary ion mass spectrometry (ToF-SIMS) is an effective technique. The mass interference between isotopes and matrix element in data interpretation makes the process complex. In this study, we have investigated the doping concentration of phosphorus in, phosphorus doped silicon thin film on glass using ToF-SIMS in the dynamic mode of operation. To overcome the mass interference between phosphorus and silicon isotopes, the quantitative analysis of counts to concentration conversion was done following two routes, standard relative sensitivity factor (RSF) and SIMetric software estimation. Phosphorus doped silicon thin film of 180 nm was grown on glass substrate using hot wire chemical vapor deposition technique for possible applications in optoelectronic devices. Using ToF-SIMS, the phosphorus-31 isotopes were detected in the range of 10¹~10⁴ counts. The silicon isotopes matrix element was measured from p-type silicon wafer from a separate measurement to avoid mass interference. For the both procedures, the phosphorus concentration versus depth profiles were plotted which agree with a percent difference of about 3% at 100 nm depth. The concentration of phosphorus in silicon was determined in the range of 10¹⁹~10²¹ atoms/cm³. The technique will be useful for estimating distributions of various dopants in the silicon thin film grown on glass using ToF-SIMS overcoming the mass interference between isotopes.

• Journal of the Korean Society of Industry Convergence
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• v.25 no.3
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• pp.333-340
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• 2022

Recently, the use of large-capacity secondary batteries for electric vehicles is rapidly increasing, and accordingly, the demand for technologies and equipment for battery reliability evaluation is increasing significantly. The existing short circuit test equipment for evaluating the stability of the existing secondary battery consists of relays, MCs, and switches, so when a large current is energized during a short circuit, contact fusion failures occur frequently, resulting in high equipment maintenance and repair costs. There was a disadvantage that repeated testing was impossible. In this paper, we developed an electronic short circuit test device that realizes stable switching operation when a large-capacity power semiconductor switch is energized with a large current, and applied smart ICT technology to this electronic short circuit stability test system to achieve high speed and high precision through communication with the master. It is expected that the inspection history management system based on data measurement, database format and user interface will be utilized as essential inspection process equipment.

• Annual Conference of KIPS
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• 2022.05a
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• pp.477-480
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• 2022

반도체 성능 향상으로 신호를 전달하는 회로의 단위가 마이크로 미터에서 나노미터로 미세화되어 선폭(linewidth)이 점점 좁아지고 있다. 이러한 변화는 검출해야 할 불량의 크기가 작아지고, 정상 공정상태와 비정상 공정상태의 차이도 상대적으로 감소되어, 공정오차 및 공정조건의 허용범위가 축소되었음을 의미한다. 따라서 검출해야 할 이상징후 탐지가 더욱 어렵게 되어, 높은 정밀도와 해상도를 갖는 검사공정이 요구되고 있다. 이러한 이유로, 미세 공정변화를 파악할 수 있는 신규 검사 및 계측 공정이 추가되어 TAT(Turn-around Time)가 증가하게 되었고, 웨이퍼가 가공되어 완제품까지 도달하는데 필요한 공정시간이 증가하여 제조원가 상승의 원인으로 작용한다. 본 논문에서는 웨이퍼의 검계측 데이터가 아닌, 제조공정 과정에서 발생하는 다양한 센서 및 장비 데이터를 기반으로 웨이퍼 제조 결과가 양품인지 그렇지 않으면 불량인지 구별할 수 있는 가상계측 모델을 제안한다. 기계학습의 여러 알고리즘 중에서 다양한 장점을 갖는 XGBoost 알고리즘을 이용하여 예측모델을 구축하였고, 데이터 전처리(data-preprocessing), 주요변수 추출(feature selection), 모델 구축(model design), 모델 평가(model evaluation)의 순서로 연구를 수행하였다. 결과적으로 약 94% 이상의 정확성을 갖는 모형을 구축하는데 성공하였으나 더욱 높은 정확성을 확보하기 위해서는 반도체 공정과 관련된 Domain Knowledge 를 반영한 모델구축과 같은 추가적인 연구가 필요하다.