• Title/Summary/Keyword: Semiconductor Process

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Process Conditions Optimizing the Yield of Power Semiconductors (전력반도체의 수율향상을 위한 최적 공정조건 결정에 관한 연구)

  • Koh, Kwan Ju;Kim, Na Yeon;Kim, Yong Soo
    • Journal of Korean Society for Quality Management
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    • v.47 no.4
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    • pp.725-737
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    • 2019
  • Purpose: We used a data analysis method to improve semiconductor manufacturing yield. We defined and optimized important factors and applied our findings to a real-world process. The semiconductor industry is very cost-competitive; our findings are useful. Methods: We collected data on 15 independent variables and one dependent variable (yield); we removed outliers and missing values. Using SPSS Modeler ver. 18.0, we analyzed the data both continuously and discretely and identified common factors. Results: We optimized two independent variables in terms of process conditions; yield improved. We used DS Leak software to model netting and Contact CD software to model meshes. DS Leak shows smaller the better characterisrics and Contact CD shows normal the best characteristics Conclusion: Various efforts have been made to improve semiconductor manufacturing yields, and many studies have created models or analyzed various characteristics. We not only defined important factors but also showed how to control processing to improve semiconductor yield.

Semiconductor laser-based absorption spectroscopy for monitoring physical vapor deposition process (증기증착 공정 감시를 위한 반도체 레이저 흡수 분광학)

  • 정의창;송규석;차형기
    • Journal of the Korean Vacuum Society
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    • v.13 no.2
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    • pp.59-64
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    • 2004
  • A study on the semiconductor laser-based atomic absorption spectroscopy was performed for monitoring physical vapor deposition process. Gadolinium metal was vaporized with a high evaporation rate by electron beam heating. Real-time atomic absorption spectra were measured by using tunable semiconductor laser beam at 770-794 nm (center wavelength of 780 nm) and its second harmonic at 388-396 nm. Atomic densities of metal vapor can be calculated from the absorption spectra measured. We plot the atomic densities as a function of the electron beam power and compare with the evaporation rates measured by quartz crystal monitor. We demonstrate that the semiconductor laser-based spectroscopic system developed in this study can be applied to monitor the physical vapor deposition process for other metals such as titanium.

Fourier Transform Infrared Spectroscopic Analysis of the Silylated Resist on Silicon Wafers in Semiconductor Lithographic Process (반도체 사진공정에서 실리콘 웨이퍼 위의 Silylated Resist의 Fourier 변환 적외선 분광분석)

  • Kang, Sung Chul;Kim, Su Jong;Son, Min Young;Park, Chun Geun
    • Analytical Science and Technology
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    • v.5 no.4
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    • pp.455-464
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    • 1992
  • Using FT-IR, we determined the depth of silylated layers produced from various gas-phase-silylation conditions was proposed by using Fourier Transform Infrared (FT-IR) spectroscopic analysis. The depth of silylated layer was determined from absorbance measurments of the significant peaks (Si-O-ph, Si-C, Si-H) of FT-IR spectra with background spectrum subtraction method. And the results were compared with thickness measurments of SEM. The results were well agree with SEM. It found to be well suited for determining silylation process window.

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A Study on Electron-beam Lithography Simulation for Resist Surface Roughness Prediction (Resist 표면 거칠기 예측을 위한 전자빔 리소그라피 시뮬레이션에 관한 연구)

  • Kim, Hak;Han, Chang-Ho;Lee, Ki-Yong;Lee, Woo-Jin;Chun, Kuk-Jin
    • Proceedings of the IEEK Conference
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    • 2002.06b
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    • pp.45-48
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    • 2002
  • This paper discusses the surface roughness of negative chemically amplified resists, SAL601 exposed by I-beam direct writing. system. Surface roughness, as measured by atomic force microscopy, have been simulated and compared to experimental results. Molecular-scale simulator predicts the roughness dependence on material properties and process conditions. A chemical amplification is made to occur in the resists during PEB process. Monte-Carlo and exposure simulations are used as the same program as before. However, molecular-scale PEB simulation has been remodeled using a two-dimensional molecular lattice representation of the polymer matrix. Changes in surface roughness are shown to correlate with the dose of exposure and tile baking time of PEB process. The result of simulation has a similar tendency with that of experiment.

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Design of Non-flammable Mixed Refrigerant Joule-Thomson Refrigerator for Semiconductor Etching Process (반도체 식각공정을 위한 비가연성 혼합냉매 줄톰슨 냉동기 설계)

  • Lee, Cheonkyu;Kim, Jin Man;Lee, Jung-Gil
    • Journal of the Semiconductor & Display Technology
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    • v.21 no.2
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    • pp.144-149
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    • 2022
  • A cryogenic Mixed Refrigerant Joule-Thomson refrigeration cycle was designed to be applied to the semiconductor etching process with non-flammable constituents. 3-stage cascade refrigerator, single mixed refrigerant Joule-Thomson refrigerator, and 2-stage cascade type mixed refrigerant Joule-Thomson refrigerator are analyzed to figure out the coefficient of performance. Non-flammable mixture of argon(Ar), tetrafluoromethane(R14), trifluoromethane (R23) and octafluoropropane(R218) were utilized to analyze the refrigeration cycle efficiency. The designed refrigeration cycle was adapted to cool down the coolant of HFE7200(Ethoxy-nonafluorobutane, C4F9OC2H5) with certain constraints. Maximum coefficient of performance of the refrigeration system is obtained as 0.289 for the cooling temperature lower than -100℃. The detailed result of the coefficient of performance according to the mixture composition is discussed in this study.

Simulation Studies on the Super-junction MOSFET fabricated using SiGe epitaxial process (SiGe 에피 공정기술을 이용하여 제작된 초 접합 금속-산화막 반도체 전계 효과 트랜지스터의 시뮬레이션 연구)

  • Lee, Hoon-Ki;Park, Yang-Kyu;Shim, Kyu-Hwan;Choi, Chel-Jong
    • Journal of the Semiconductor & Display Technology
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    • v.13 no.3
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    • pp.45-50
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    • 2014
  • In this paper, we propose a super-junction MOSFET (SJ MOSFET) fabricated through a simple pillar forming process by varying the Si epilayer thickness and doping concentration of pillars using SILVACO TCAD simulation. The design of the SJ MOSFET structure is presented, and the doping concentration of pillar, breakdown voltage ($V_{BR}$) and drain current are analyzed. The device performance of conventional Si planar metal-oxide semiconductor field-effect transistor(MOSFET), Si SJ MOSFET, and SiGe SJ MOSFET was investigated. The p- and n-pillars in Si SJ MOSFET suppressed the punch-through effect caused by drain bias. This lead to the higher $V_{BR}$ and reduced on resistance of Si SJ MOSFET. An increase in the thickness of Si epilayer and decrease in the former is most effective than the latter. The implementation of SiGe epilayer to SJ MOSFET resulted in the improvement of $V_{BR}$ as well as drain current in saturation region, when compared to Si SJ MOSFET. Such a superior device performance of SiGe SJ MOSFET could be associated with smaller bandgap of SiGe which facilitated the drift of carriers through lower built-in potential barrier.

ADP DRY ETCHER TECHNOLOGY (ADP Dry Etcher 장비개발의 현황)

  • Kim, Jeong-Tae
    • Proceedings of the Korean Society Of Semiconductor Equipment Technology
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    • 2008.05a
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    • pp.23-29
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    • 2008
  • - High Density Plasma Source-CCP-Dual/Triple, RF Frequency Control - Radical/Flux Analysis - Low Pressure Process - Chamber Design (Process gap/Wall gap) - Chamber Temp. Control. - ESC Dielectric Materials - Uniform Gas Injection

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Study on Evaporating Process Modeling for Estimation of Thin-film Thickness Distribution (박막두께 예측을 위한 증착 공정 모델링에 관한 연구)

  • Lee Eung-Ki;Lee Dong-Eun;Lee Sook-Han
    • Proceedings of the Korean Society Of Semiconductor Equipment Technology
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    • 2006.05a
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    • pp.156-159
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    • 2006
  • In order to design an evaporation system, geometric simulation of film thickness distribution profile is required. In this paper, a geometric modeling algorithm is introduced for process simulation of the evaporating process. The physical fact of the evaporating process is modeled mathematically. Based on the developed method, the thickness of the thin-film layer can be successfully controlled.

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TFT LCD 용 Power Inductor Full Automation Winding/Welding System 개발

  • 이우영;진경복;김경수
    • Proceedings of the Korean Society Of Semiconductor Equipment Technology
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    • 2004.05a
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    • pp.154-158
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    • 2004
  • Power inductor is usually used in the field of the power circuit of a cellular phone, TFT LCD module etc.. This paper presents the development process of Power Inductor Full Automation Winding/Welding System for TFT LCD. This process, the process algorithm, high precision welding current control, design of welding head, high speed, high precision feeding mechanism, and user interface process control program technologies are included.

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A Simulation Study for Analyzing an on-Demand Semiconductor Wafer Process (주문형 반도체 웨이퍼 공정분석을 위한 시뮬레이션 연구)

  • Kim, Ki-Young;Lee, Jung-Ho;Kang, Chang-Ho;Kim, Kap-Hwan
    • IE interfaces
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    • v.18 no.1
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    • pp.22-34
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    • 2005
  • This paper introduces a simulation model which is based on the process analysis of a semiconductor company. The objective of the simulation modelis not only to estimate the overall performancesof the company but also to evaluate the performances of various operation rules for shop floor control. First, in order to develop the simulation model, a time study is performed for each process after analyzing the processes for the company. Second, by using ARENA, a simulation model is constructed based on the process analysis and the time study. After the simulation model is tested and run, its results are discussed.