• 마이크로전자및패키징학회지
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• 제20권4호
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• pp.35-39
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• 2013

반도체센서의 응력에 따른 전기적 특성을 프로브 스테이션 위에서 측정하기 위해 소형 4점 굽힘 장치를 개발하였다. 4점 굽힘 장치는 $60{\times}83mm^2$의 면적을 갖는 소형 장치로 마이크로미터를 통해 정확한 변위를 인가함으로서 가해진 응력을 구할 수 있다. 유한요소해석법을 사용하여 기기의 오차를 예측하고 정밀도를 향상하였다. 실험적으로는 4점 굽힘 장치로 인가된 응력을 검증하기 위해 스트레인 게이지로 검증하였다.

• 한국마이크로전자및패키징학회:학술대회논문집
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• 한국마이크로전자및패키징학회 2002년도 International Symposium
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• pp.219-225
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• 2002

This paper presents a novel "bumpless flip chip package"for cost! performance driven devices. Using the conventional electroplating and etching processes, this package enables the production of fine pitch BGA up to 256 I/O with single layer routing. An array of circuitry down to $25-50{\mu}{\textrm}{m}$ line/space is fabricated to fan-in and fan-out of the bond pads without using bumps or substrate. Various types of joint methods can be applied to connect the fine trace and the bond pad directly. The resin-filled terminal provides excellent compliancy between package and the assembled board. More interestingly, the thin film routing is similar to wafer level packaging whereas the fan-out feature enables high lead count devices to be accommodated in the BGA format. Details of the design concepts and processing technology for this novel package are discussed. Trade offs to meet various cost or performance goals for selected applications are suggested. Finally, the importance of design integration early in the technology development cycle with die-level and system-level design teams is highlighted as critical to an optimal design for performance and cost.

• 전자공학회논문지A
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• 제33A권2호
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• pp.148-162
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• 1996

Bonding wires for high frequency device packaging have dominant parasitic inductances which limit the performance of semiconductor lasers. In this paper, the inductance sof bonding wires are claculated by the method of moments with incorporation of ohmic loss, and the wideband modulation characteristics are analyzed for ddifferent wire lengths and structures. We observed the modulation bandwidth for 1mm-length bonding wire lengths and structures. We observed the modulation bandwidth for 1mm-length bonding wire is 7 GHz wider than that for 2mm-length bonding wire. We also observed th estatic inductance calculation results in dispersive deviation of the parasitic inductance and the modulation characteristics from the wideband moment methods calculations. The angled bonding wire has much less parasitic inductance and improves the modulation bandwidth more than 6 GHz. This calculation resutls an be widely used for designing and packaging of high-speed semiconductor device.

• 한국마이크로전자및패키징학회:학술대회논문집
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• 한국마이크로전자및패키징학회 1999년도 1st Korea-Japan Advanced Semiconductor Packaging Technology Seminar
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• pp.127-154
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• 1999

Interconnect - Wire bonding-> Flip chip interconnect ; At research step, Au stud bump bonding seems to be more proper .Package -Plastic package-> $Z_{0}$ controlled land grid package -Flip Chip will be used for RF ICs and CSP for digital ICs -RF MCM comprised of bare active devices and integrated passive components -Electrical design skills are much more required in RF packaging .Passive Component -discrete-> integrated -Both of size and numbers of passive components must be reduced

• 한국마이크로전자및패키징학회:학술대회논문집
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• 한국마이크로전자및패키징학회 2002년도 춘계 기술심포지움 논문집
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• pp.1-6
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• 2002

It is very important to foresee the main stream of technology development in the future. Packaging related manufacturers in equipment and materials focused their strength on products sharing big portion of world markets. As a result, domestic supply sources for packaging materials and equipment has been increased, but the manufacturer's capital and manpower is so limited to develop high technology machinery and high functional materials. The current status of packaging infrastructures in Korea is reviewed statistically. The hot issues in packaging arena are now in wafer level packaging, 3D packaging, and ultra-thin packaging. In addition, the recent advancement in microelectronics packaging technology is also covered.

• 한국마이크로전자및패키징학회:학술대회논문집
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• 한국마이크로전자및패키징학회 2001년도 3rd Korea-Japan Advanced Semiconductor Packaging Technology Seminar
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• pp.183-192
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• 2001

1- Buildup PCB technology is utilized to a bare chip attach substrate technology for packaging of semiconductor chip 2- Requirement for the substrate design rule is described in SIA International Technology Roadmap for Semiconductor. 3- There are seven fabrication methods of build-up technology. 4- Coating and lamination for resin and photo, and laser for micro via hope processes are available. Below $50\mu\textrm{m}$ in diameter is possible. 5- Fine pitch lines down to $30\mu\textrm{m}$ can be achieved by pattern plating with better electrical property. 6- Dielectric loss reduction is a key material improvement item for next generation build-up technology. 7- High band width up to 512 GB/s is possible with current wiring groundrule.

• 반도체디스플레이기술학회지
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• 제1권1호
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• pp.15-19
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• 2002

A new vacuum packaging process in wafer level is developed for the surface micromachining devices using glass silicon anodic bonding technology. The inside pressure of the packaged device was measured indirectly by the quality factor of the mechanical resonator. The measured Q factor was about 5$\times10^4$ and the estimated inner pressure was about 1 mTorr. And it is also possible to change the inside pressure of the packaged devices from 2 Torr to 1 mTorr by varying the amount of the Ti gettering material. The long-term stability test is still on the way, but in initial characterization, the yield is about 80% and the vacuum degradation with time was not observed.

• 한국전자파학회지:전자파기술
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• 제24권2호
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• pp.23-34
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• 2013

Over the past several decades in the microelectronics industry, devices have gotten smaller, thinner, and lighter, without any accompanying degradation in quality, performance, and reliability. One permanent and deniable trend in packaging as well as wafer fabrication industry is system integration. The proliferating options for system integration, recently, are driving change across the overall semiconductor industry, requiring more investment in developing, ramping and supporting new die-, wafer- and board-level solution. The trend toward 3D system integration and miniaturization in a small form factor has accelerated even more with the introduction of smartphones and tablets. In this paper, the key issues and state of the art for system integration in the packaging process are introduced, especially, focusing on ease transition to next generation packaging technologies like through silicon via (TSV), 3D wafer-level fan-out (WLFO), and chip-on-chip interconnection. In addition, effective solutions like fine pitch copper pillar and MEMS packaing of both advanced and legacy products are described with several examples.

• 한국신뢰성학회:학술대회논문집
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• 한국신뢰성학회 2001년도 정기학술대회
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• pp.239-244
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• 2001

Today, Ultrasonic is used as an important non-destructive test tool of semiconductor reliability evaluation and failure analysis. The semiconductor packaging trend goes to develop thin package, this trend makes difficult to inspect to defect in semiconductor package. One of the important problem in all semiconductor is moisture absorption in the atmosphere. This moisture causes crack or delamination to package when the semiconductor package is soldered on PCB. Reliability evaluation of semiconductor's object is investigating the effect of this moisture. For that reason, this study is investigating the effect of this moisture and reliability evaluation of semiconductor after preconditioning test and scanning acoustic microscope.

• 마이크로전자및패키징학회지
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• 제12권1호
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• pp.59-63
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• 2005

금속-강유전체-반도체 전계효과 트랜지스터 (MFS/MFISFET)의 동작 특성을 technology computer-aided design (TCAD)과 simulation program with integrated circuit emphasis (SPICE)를 결합하여 전산모사하는 방법을 제시하였다. 복잡한 강유전체의 동작 특성을 수치해석을 이용하여 해석한 다음, 이를 이용하여 금속-강유전체-반도체 구조에서 반도체 표면에 인가되는 표면 전위를 계산하였다. 계산된 TCAD 변수인 표면 전위를 전계효과 트랜지스터의 SPICE 모델에서 구한 표면 전위와 같다고 보고게이트 전압에 따른 전류전압 특성을 구할 수 있었다. 이와 같은 방법은 향후 MFS/MFISFET를 이용한 메모리소자의 집적회로 설계에 매우 유용하게 적용될 수 있을 것이다.