• Journal of the Microelectronics and Packaging Society
• /
• v.21 no.3
• /
• pp.7-17
• /
• 2014

Power electronics modules are semiconductor components that are widely used in airplanes, trains, automobiles, and energy generation and conversion facilities. In particular, insulated gate bipolar transistors(IGBT) have been widely utilized in high power and fast switching applications for power management including power supplies, uninterruptible power systems, and AC/DC converters. In these days, IGBT are the predominant power semiconductors for high current applications in electrical and hybrid vehicles application. In these application environments, the physical conditions are often severe with strong electric currents, high voltage, high temperature, high humidity, and vibrations. Therefore, IGBT module packages involves a number of challenges for the design engineer in terms of reliability. Thermal and thermal-mechanical management are critical for power electronics modules. The failure mechanisms that limit the number of power cycles are caused by the coefficient of thermal expansion mismatch between the materials used in the IGBT modules. All interfaces in the module could be locations for potential failures. Therefore, a proper thermal design where the temperature does not exceed an allowable limit of the devices has been a key factor in developing IGBT modules. In this paper, we discussed the effects of various package materials on heat dissipation and thermal management, as well as recent technology of the new package materials.

• Journal of the Microelectronics and Packaging Society
• /
• v.26 no.3
• /
• pp.59-62
• /
• 2019

In this study, we have developed solution-processed, F-doped In-Ga-Zn-O semiconductors and investigated their applications to thin-film transistors. In order for forming the appropriate channel layer, precursor solutions were formulated by dissolving the metal salts in the designated solvent and an additive, ammonium fluoride, was incorporated additionally as a chemical modifier. We have studied thermal and chemical contributions by a thermal annealing and an incorporation of chemical modifier, from which it was revealed that electrical performances of the thin-film transistors comprising the channel layer annealed at a low temperature can be improved significantly along with an addition of ammonium fluoride. As a result, when the 20 mol% fluorine was incorporated into the semiconductor layer, electrical characteristics were accomplished with a field-effect mobility of $1.2cm^2/V{\cdot}sec$ and an $I_{on}/_{off}$ of $7{\times}10^6$.

• Journal of the Microelectronics and Packaging Society
• /
• v.25 no.4
• /
• pp.59-66
• /
• 2018

In this paper, we analyzed the usefulness of single-structured printed circuit board (PCB) modeling by using numerical analysis to model the PCB structure applied to a package for semiconductor purposes and applying modeling assuming a single structure. PCBs with circuit layer of 3rd and 4th were used for analysis. In addition, measurements were made on actual products to obtain material characteristics of a single structure PCB. The analysis results showed that if the PCB was modeled in a single structure compared to a multi-layered structure, the warpage analysis results resulting from modeling the PCB structure would increase and there would be a significant difference. In addition, as the circuit layer of the PCB increased, the mechanical properties of the PCB, the elastic coefficient and inertia moment of the PCB increased, decreasing the package's warpage.

• Journal of the Microelectronics and Packaging Society
• /
• v.29 no.2
• /
• pp.1-10
• /
• 2022

Recently, semiconductor devices have been used in many fields owing to various applications of mobile electronics, wearable and flexible devices and substrates. During the semiconductor chip bonding process, the mismatch of coefficient of therm al expansion (CTE) between the substrate and the solder, and the excessive heat applied to the entire substrate and components affect the performance and reliability of the device. These problems can cause warpage and deterioration of long-term reliability of the electronic packages. In order to improve these issues, many studies on low-melting temperature solders, which is capable of performing a low-temperature process, have been actively conducted. Among the various low-melting temperature solders, such as Sn-Bi and Sn-In, Sn-58Bi solder is attracting attention as a promising low-temperature solder because of its advantages such as high yield strength, moderate mechanical property, and low cost. However, due to the high brittleness of Bi, improvement of the Sn-Bi solder is needed. In this review paper, recent research trends to improve the mechanical properties of Sn-Bi solder by adding trace elements or particles were introduced and compared.

• Journal of the Microelectronics and Packaging Society
• /
• v.30 no.1
• /
• pp.63-70
• /
• 2023

Today, the importance of power semiconductors continues to increase due to serious environmental pollution and the importance of energy. Particularly, SiC-MOSFET, which is one of the wide bandgap (WBG) devices, has excellent high voltage characteristics and is very important. However, since the electrical properties of SiC-MOSFET are heatsensitive, thermal management through a package is necessary. In this paper, we propose an insulated metal substrate (IMS) method rather than a direct bonded copper (DBC) substrate method used in conventional power semiconductors. IMS is easier to process than DBC and has a high coefficient of thermal expansion (CTE), which is excellent in terms of cost and reliability. Although the thermal conductivity of the dielectric film, which is an insulating layer of IMS, is low, the low thermal conductivity can be sufficiently overcome by allowing a process to be very thin. Electric-thermal co-simulation was carried out in this study to confirm this, and DBC substrate and IMS were manufactured and experimented for verification.

• Journal of the Microelectronics and Packaging Society
• /
• v.29 no.4
• /
• pp.83-87
• /
• 2022

Recently, as the thickness of the semiconductor package becomes thinner, warpage has become a major issue. Since the warpage is caused by differences in material properties between package components, it is essential to precisely evaluate the material properties of the EMC(Epoxy molding compound), one of the main components, to predict the warpage accurately. Especially, the cure shrinkage of the EMC is generated during the curing process, and among them, the effective cure shrinkage that occurs after the gelation point is a key factor in warpage. In this study, the gelation point of the EMC was defined from the dissipation factor measured using the dielectric sensor during the curing process similar with actual semiconductor package. In addition, DSC (Differential scanning calorimetry) test and rheometer test were conducted to analyze the dielectrometry measurement. As a result, the dielectrometry was verified to be an effective method for monitoring the curing status of the EMC. Simultaneously, the strain transition of the EMC during the curing process was measured using the FBG (Fiber Bragg grating) sensor. From these results, the effective cure shrinkage of the EMC during the curing process was measured.

• Journal of the Microelectronics and Packaging Society
• /
• v.31 no.1
• /
• pp.35-42
• /
• 2024

Recently, with the miniaturization and high integration of semiconductor chips, the bump bridge phenomenon caused by fine pitches is drawing attention as a problem. Accordingly, Cu pillar bump, which can minimize the bump bridge phenomenon, is widely applied in the semiconductor package industry for fine pitch applications. When exposed to a high-temperature environment, the thickness of the intermetallic compound (IMC) formed at the joint interface increases, and at the same time, Kirkendall void is formed and grown inside some IMC/Cu and IMC interfaces. Therefore, it is important to control the excessive growth of IMC and the formation and growth of Kirkendall voids because they weaken the mechanical reliability of the joints. Therefore, in this study, isothermal aging evaluation of Cu pillar bump joints with a CS (Cu+ Sn-1.8Ag Solder) structure was performed and the corresponding results was reported.

• Journal of the Semiconductor & Display Technology
• /
• v.9 no.2
• /
• pp.33-39
• /
• 2010

The moisture absorption properties such as diffusion coefficient and moisture content ratio of liquid type epoxy resin systems with the filler were investigated. Bisphenol A type and Bisphenol F type epoxy resin, Kayahard MCD as hardener and 2-methylimidazole as catalyst were used in these epoxy resin systems. The nano-sized spherical type fused silica as filler were used in order to study the moisture absorption properties of these liquid type epoxy encapsulant according to the change of filler size. The temperature of glass transition (Tg) of these epoxy resin systems was measured using Dynamic Scanning Calorimeter (DSC), and the moisture absorption properties of these epoxy resin systems according to the change of time were observed at $85^{\circ}C$ and 85% relative humidity condition using a thermo-hygrostat. The diffusion coefficients in these systems were calculated in terms of modified Crank equation based on Ficks' law. An increase of Tg and diffusion coefficient with filler size in these systems can be observed, which are attributed to the increase of free volume with Tg. The change of maximum moisture absorption ratio according to the filler size and filler content cannot be observed; however, the diffusion coefficients of these systems decreased with filler content. The diffusion via free volume is dominant in the epoxy resin systems with low nano-sized filler content; however, the diffusion with the interaction of absorption according the increase of the filler surface area is dominant in the liquid type epoxy encapsulant with high nano-sized filler content.

• Journal of the Korea Society for Simulation
• /
• v.18 no.2
• /
• pp.65-75
• /
• 2009

The semiconductor manufacturing process normally includes a great number of complex sequential steps those are related with various types of equipment. Such equipments are installed with the mixed patterns of serial or parallel structures while considering a number of engineering or environmental factors at the same time. It is thus extremely difficult to change the layout after installation due to expensive costs and other related factors. Because of these reasons, a new investment or layout change, which is usually caused by the production policy such as product mix or production quantity, must be carefully considered. This case study introduces a simulation conducted in a semiconductor parts production company which produces the Board on Chip (BOC)-type of packaging substrate and has plans to change the facility layout. For this study, we used $QUEST^{(R)}$ for simulation modeling and evaluated various strategies which may cause layout changes. Further, the Analytic Hierarchy Process (AHP) is applied to select the best strategy from several alternatives with multiple decision criteria.

• Journal of the Semiconductor & Display Technology
• /
• v.22 no.4
• /
• pp.124-130
• /
• 2023

Recently, fan out wafer level packaging, which enables high integration, miniaturization, and low cost, is being rapidly applied in the semiconductor industry. In particular, FOWLP is attracting attention in the mobile and Internet of Things fields, and is recognized as a core technology that will lead to technological advancements such as 5G, self-driving cars, and artificial intelligence in the future. However, as chip density and package size within the package increase, FOWLP warpage is emerging as a major problem. These problems have a direct impact on the reliability and electrical performance of semiconductor products, and in particular, cause defects such as vacuum leakage in the manufacturing process or lack of focus in the photolithography process, so technical demands for solving them are increasing. In this paper, warpage simulation according to the thickness of FOWLP material was performed using finite element analysis. The thickness range was based on the history of similar packages, and as a factor causing warpage, the curing temperature of the materials undergoing the curing process was applied and the difference in deformation due to the difference in thermal expansion coefficient between materials was used. At this time, the stacking order was reflected to reproduce warpage behavior similar to reality. After performing finite element analysis, the influence of each variable on causing warpage was defined, and based on this, it was confirmed that warpage was controlled as intended through design modifications.