• Journal of the Microelectronics and Packaging Society
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• v.20 no.2
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• pp.1-9
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• 2013

Recently flexible electronic devices have attracted a great deal of attention because of new application possibilities including flexible display, flexible memory, flexible solar cell and flexible sensor. In particular, development of flexible memory is essential to complete the flexible integrated systems such as flexible smart phone and wearable computer. Research of flexible memory has primarily focused on organic-based materials. However, organic flexible memory has still several disadvantages, including lower electrical performance and long-term reliability. Therefore, emerging research in flexible electronics seeks to develop flexible and stretchable technologies that offer the high performance of conventional wafer-based devices as well as superior flexibility. Development of flexible memory with inorganic silicon materials is based on the design principle that any material, in sufficiently thin form, is flexible and bendable since the bending strain is directly proportional to thickness. This article reviews progress in recent technologies for flexible memory and flexible electronics with inorganic silicon materials, including transfer printing technology, wavy or serpentine interconnection structure for reducing strain, and wafer thinning technology.

• Journal of the Microelectronics and Packaging Society
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• v.11 no.1
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• pp.43-47
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• 2004

We have been using Moisture Barrier Bags for dry packing of semiconductor packages to prevent moisture from absorbing during shipping. Moisture barrier bag material is required to be waterproof, vapor proof and offer superior ESD (Electro-static discharge) and EMI shielding. Also, the bag should be formed easily to the shape of products for vacuum packing while providing excellent puncture resistance and offer very low gas ＆ moisture permeation. There are some problems like pinholes and punctured bags after sealing and before the surface mount process. This failure may easily result in package pop corn crack during board mounting. The bags should be developed to meet the requirements of excellent electrical and physical properties by means of optimization of their raw material composition and their thickness. This study investigates the performance of moisture barrier bags by characterization of their mechanical endurance, tensile strength and through thermal analysis. By this study, we arrived at a robust material composition (polyester/Aluminate) for better packing.

• Journal of the Microelectronics and Packaging Society
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• v.21 no.1
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• pp.13-17
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• 2014

The direct-patternable $SnO_2$ thin film was successfully fabricated by photochemical metal-organic deposition. The composition and chemical bonding state of $SnO_2$ thin film were analyzed by using X-ray photoelectron spectroscopy (XPS) from the surface to the interface with Si substrate. XPS depth profiling analysis allowed the determination of the atomic composition in $SnO_2$ film as a function of depth through the evolution of four elements of C 1s, Si 2p, Sn 3d, and O 1s core level peaks. At the top surface, nearly stoichiometric $SnO_2$ composition (O/Sn ratio is 1.92.) was observed due to surface oxidation but deficiency of oxygen was increased to the interface of patterned $SnO_2/Si$ substrate where the O/Sn ratio was about 1.73~1.75 at the films. This O deficient state of the film may act as an n-type semiconductor and allow $SnO_2$ to be applied as a transparent electrode in optoelectronic applications.

• Journal of the Microelectronics and Packaging Society
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• v.15 no.2
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• pp.69-73
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• 2008

This article shows that the susceptibility of the device pattern to thermal stress-induced damage has a strong dependence on its proximity to the device comer in semiconductor devices utilizing lead-on-chip (LOC) die attach technique. The result, as explained based on numerical calculation and experiment, indicateds that the stress-driven damage potential of the passivation layer is the highest at the device comer. Thus, the bonding pads, which are very susceptible to passivation damage, should be designed to be located along the central region rather than the peripheral region of the device.

• Journal of the Microelectronics and Packaging Society
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• v.8 no.4
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• pp.67-72
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• 2001

An Effort has been made to more accurately analyze the flow in the chip cavity, particularly to model the flow through the openings in the leadframe and correctly treat the thermal boundary condition at the leadframe. The theoretical analysis of the flow has been done by using the Hele-Shaw approximation in each cavity separated by a leadframe. The cross-flow through the openings in the leadframe has been incorporated into the Hele-Shaw formulation as a mass source term. The optimization program based on the complex method integrated with flow analysis program has been successfully used to obtain the optimal filling conditions to avoid short shot.

• Journal of the Microelectronics and Packaging Society
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• v.26 no.3
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• pp.15-22
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• 2019

In these days, importance of the power electronic devices and modules keeps increasing due to electric vehicles and energy saving requirements. However, current silicon-based power devices showed several limitations. Therefore, wide band gap (WBG) semiconductors such as SiC, GaN, and $Ga_2O_3$ have been developed to replace the silicon power devices. WBG devices show superior performances in terms of device operation in harsh environments such as higher temperatures, voltages and switching speed than silicon-based technology. In power devices, the reliability of the devices and module package is the critically important to guarantee the normal operation and lifetime of the devices. In this paper, we reviewed the recent trends of the power devices based on WBG semiconductors as well as expected future technology. We also presented an overview of the recent package module and fabrication technologies such as direct bonded copper and active metal brazing technology. In addition, the recent heat management technologies of the power modules, which should be improved due to the increased power density in high temperature environments, are described.

• Journal of the Microelectronics and Packaging Society
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• v.29 no.3
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• pp.37-42
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• 2022

Recently, the semiconductor package structures are becoming thinner and more complex. As the thickness decrease, interfacial delamination due to material mismatch can be further maximized, so the reliability of interface is a critical issue in industry field. Especially, the polymers, which are widely used in semiconductor packaging, are significantly affected by the temperature and moisture. Therefore, in this study, the delamination prediction at the interface of package structure was performed through finite element analysis considering the moisture absorption and desorption under the various temperature conditions. The material properties such as diffusivity and saturated moisture content were obtained from moisture absorption test. The hygro-swelling coefficients of each material were analyzed through TMA and TGA after the moisture absorption. The micro-shear test was conducted to evaluate the adhesion strength of each interface at various temperatures considering the moisture effect. The finite element analysis of interfacial delamination was performed that considers both deformation due to temperature and moisture absorption. Consequently, the interfacial delamination was successfully predicted in consideration of the in-situ moisture desorption and temperature behavior during the reflow process.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.431-432
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• 2012

In the era of 20 nm scaled semiconductor volume manufacturing, Microelectronics Manufacturing Engineering Education is presented in this paper. The purpose of microelectronic engineering education is to educate engineers to work in the semiconductor industry; it is therefore should be considered even before than technology development. Three Microelectronics Manufacturing Engineering related courses are introduced, and how undergraduate students acquired hands-on experience on Microelectronics fabrication and manufacturing. Conventionally employed wire bonding was recognized as not only an additional parasitic source in high-frequency mobile applications due to the increased inductance caused from the wiring loop, but also a huddle for minimizing IC packaging footprint. To alleviate the concerns, chip bumping technologies such as flip chip bumping and pillar bumping have been suggested as promising chip assembly methods to provide high-density interconnects and lower signal propagation delay [1,2]. Aluminum as metal interconnecting material over the decades in integrated circuits (ICs) manufacturing has been rapidly replaced with copper in majority IC products. A single copper metal layer with various test patterns of lines and vias and $400{\mu}m$ by $400{\mu}m$ interconnected pads are formed. Mask M1 allows metal interconnection patterns on 4" wafers with AZ1512 positive tone photoresist, and Cu/TiN/Ti layers are wet etched in two steps. We employed WPR, a thick patternable negative photoresist, manufactured by JSR Corp., which is specifically developed as dielectric material for multi- chip packaging (MCP) and package-on-package (PoP). Spin-coating at 1,000 rpm, i-line UV exposure, and 1 hour curing at $110^{\circ}C$ allows about $25{\mu}m$ thick passivation layer before performing wafer level soldering. Conventional Si3N4 passivation between Cu and WPR layer using plasma CVD can be an optional. To practice the board level flip chip assembly, individual students draw their own fan-outs of 40 rectangle pads using Eagle CAD, a free PCB artwork EDA. Individuals then transfer the test circuitry on a blank CCFL board followed by Cu etching and solder mask processes. Negative dry film resist (DFR), Accimage$^{(R)}$, manufactured by Kolon Industries, Inc., was used for solder resist for ball grid array (BGA). We demonstrated how Microelectronics Manufacturing Engineering education has been performed by presenting brief intermediate by-product from undergraduate and graduate students. Microelectronics Manufacturing Engineering, once again, is to educating engineers to actively work in the area of semiconductor manufacturing. Through one semester senior level hands-on laboratory course, participating students will have clearer understanding on microelectronics manufacturing and realized the importance of manufacturing yield in practice.

• Journal of Information Display
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• v.2 no.3
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• pp.66-71
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• 2001

MCFEDs (MOSFET-Contoolled Field Emission Displays) were fabricated to evaluate the validity of MCFEA for display application. The electrical properties of FEAs (Field Emitter Arrays), HVMOSFETs (High-Voltage MOSFETs), and MCFEAs (MOSFET-Controlled Field Emitter Arrays) were measured. The extraction gate voltage of the FEAs to obtain the anode current of 10 nA/tip was around 71 V. The breakdown voltages of the HVMOSFETs were above 81 V for all the samples. The I-V characteristics of the MCFEAs showed that the emission currents of the FEAs were well controlled depending on the control gate voltages of the HVMOSFETs. To avoid the harmful effects during the packaging process, the performance of the MCFEDs was evaluated in a high vacuum chamber. The emission images of the MCFEDs were controlled through very-through operation. From the comparison with a conventional FED, it was proven that the poor uniformity of FED could be improved through the integration with HVMOSFET.

• Journal of the Korean Society for Nondestructive Testing
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• v.21 no.6
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• pp.598-606
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• 2001

Recently, semiconductor packages trend to be thinner, which makes difficult to detect defects therein. A preconditioning test is generally performed to evaluate the reliability of semiconductor packages. The test procedure includes two scanning acoustic microscope (SAM) tests at the beginning and end of the entire test, in order to help detect physical defects such as delaminations and package cracks. In particular, of primary concern are package cracks and delaminations caused by moisture absorbed under ambient conditions. This paper discusses the failure mechanism associated with the moisture absorbed and encapsulated in semiconductors, and the use SAM to detect failures such as tracks and delaminations grown during the preconditioning test.