• Journal of the Korea Society for Simulation
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• v.21 no.2
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• pp.41-50
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• 2012

In this study we first explain details of the semiconductor manufacturing processes and cluster tools. Then we discuss the problems in current fab layout and cluster tool architecture. As a solution to these problems, we propose the ILE (In-Line EFEM) architecture in which wafer movements are conducted through interconnected EFEMs (Equipment Front End Modules) instead of AMHS (Automated Material Handling System). Then we model the pilot ILE system using discrete event simulation and analyze the cycle time. Finally we compare three different scenarios of equipment layout in the ILE system in terms of cycle time.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2008.06a
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• pp.541-542
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• 2008

• Journal of Korea Multimedia Society
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• v.3 no.4
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• pp.407-415
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• 2000

The ultimate goal of flow control in the semiconductor fabrication process, one of the most equipment-intensive and complex manufacturing process, is to reduce lead time and work in process. In this paper, we propose stand alone layout in the form of job shop using group technology to improve the Productivity and eliminate the inefficiency in FMS (flexible manufacture system). The performance of stand alone layout and in-line layout are analyzed and compared while varying number of device variable chanties. The analysis of in-line layout is obtained by examining its adoption in the memory products of semiconductor factory. The comparison is performed through simulation using ProSys; a window 95 based discrete system simulation software, as a tool for comparing performance of two proposed layouts. The comparison demonstrates that when the number of device variable change is small, in-line layout is more efficient in terms of production Quantity. However, as the number of device variable change is more than 14 times, stand alone layout prevails over in-line layout.

• Journal of Korean Society of Occupational and Environmental Hygiene
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• v.26 no.1
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• pp.1-10
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• 2016

Objectives: The aim of this study is to review the results of exposure to chemicals and to extremely low frequency(ELF) magnetic fields generated in wafer fabrication operations in the semiconductor industry. Methods: Exposure assessment studies of silicon wafer fab operations in the semiconductor industry were collected through an extensive literature review of articles reported until the end of 2015. The key words used in the literature search were "semiconductor industry", "wafer fab", "silicon wafer", and "clean room," both singly and in combination. Literature reporting on airborne chemicals and extremely low frequency(ELF) magnetic fields were collected and reviewed. Results and Conclusions: Major airborne hazardous agents assessed were several organic solvents and ethylene glycol ethers from Photolithography, arsenic from ion implantation and extremely low frequency magnetic fields from the overall fabrication processes. Most exposures to chemicals reported were found to be far below permissible exposure limits(PEL) (10% < PEL). Most of these results were from operators who handled processes in a well-controlled environment. In conclusion, we found a lack of results on exposure to hazardous agents, including chemicals and radiation, which are insufficient for use in the estimation of past exposure. The results we reviewed should be applied with great caution to associate chronic health effects.

• Journal of the Semiconductor & Display Technology
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• v.22 no.4
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• pp.26-31
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• 2023

We investigated the impact of NF₃ / H₂O remote plasma dry cleaning conditions on the SiO₂ etching rate at different preparation states during the fabrication of ultra-large-scale integration (ULSI) devices. This included consideration of factors like Si crystal orientation prior to oxidation and three-dimensional structures. The dry cleaning process were carried out varying the parameters of pressure, NF₃ flow rate, and H₂O flow rate. We found that the pressure had an effective role in controlling anisotropic etching when a thin SiO₂ layer was situated between Si₃N₄ and Si layers in a multilayer trench structure. Based on these observations, we would like to provide further guidelines for implementing the dry cleaning process in the fabrication of semiconductor devices having 3D structures.

• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.377-378
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• 2008

Morphology is one of important issues when developing a layer of CVD-W. we need to control the process more precisely that is filling gaps between BL(bit line)and DC(direct contact). Whereas we are facing to difficulties like not-filling contacts due to marginal problems in deposition and etching process. This paper is for investigating a method to resolve morphology problem with strengthening the condition of seasoning.

• Proceedings of the Korea Society for Simulation Conference
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• 1998.10a
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• pp.133-136
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• 1998

본 연구는 복잡하고 다양한 반도체 공저의 모델링을 통하여 반도체 공정 표준화 작업을 목적으로 하고 있다. 급변하는 세계 반도체 시장에서 국내 반도체 업체가 수위를 지킬 수 있는 방안은 공정의 표준화를 제시함으로써 생산업체에서의 신기술 개발에 따른 어려움을 해소하고 기술 개발과 더불어 생산관리 쪽으로의 이동에 대응할 수 있도록 하여 국제 경쟁력을 키워야 할 것이다. 본 연구의 기대효과로는 현장기술자와 장비운용자의 질적 향상을 위한 교육용 자료로의 활용이 가능하다는 것이다. Presentation Tool을 이용한 시청각 교육효과와 시뮬레이션을 이용한 Process Flow Wide View 증진은 현재 국내 반도체 업체들의 신입사원 교육 시 상당한 효과를 거둘 것이라 예상된다. 이는 생산업체에 국한되어지는 것만은 아니며 반도체 공정에 관련된 대학 학과목에서도 활용되어지리라 생각된다. 또한 Modeling & Simulation Tool을 사용하여 공정을 모델링함으로써 표준화를 만든 후 각 제조 업체들은 이러한 모델들은 이용하여 회사의 실정에 맞추어 자사에 대한 시뮬레이션을 손쉽게 수행함으로써 공정 최적화에 따른 경비 절감의 효과를 거둘 수 있을 것이다. 제품별 혹은 같은 제품이라도 Version이 다를 경우 FAB 공정가운데 약 10% 내외만이 바뀌는 점을 감안하면 본 연구를 통해 얻어지는 결과물인 Computer Model과 Simulator는 쉽게 생산현장에 적용할 수 있으리라 여겨진다.

• Proceedings of the Korean Operations and Management Science Society Conference
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• 2001.10a
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• pp.298-301
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• 2001

In semiconductor manufacturing, wafer fabrication is the most complicated and important process, which is composed of several hundreds of process steps and several hundreds of machines involved. The productivity of the manufacturing mainly depends on how well they control balance of WIP flow to achieve maximal throughput under short manufacturing cycle time. In this paper mathematical formulation is suggested for the stepper scheduling, in which cycle time reduction and maximal production is achieved.

• IE interfaces
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• v.12 no.3
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• pp.437-447
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• 1999

Modeling and system development for the fabrication process in the semiconductor manufacturing is presented in this paper. Maximization of wafer production can be achieved by the wafer flow balance under high utilization of bottleneck machines. Relatively simpler model is developed for the fabrication line by considering main characteristics of logistics. Simulation system is developed to evaluate the line performance such as balance rate, utilization, WIP amount and wafer production. Scheduling rules and input rules are suggested, and tested on the simulation system. We have shown that there exists good combination of scheduling and input rules.

• IE interfaces
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• v.22 no.1
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• pp.73-84
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• 2009

In this paper, we propose a dispatching algorithm for constructing a Factory Operating System (FOS) which can operate semiconductor fabrication factories more efficiently and effectively. We first define ten dispatching criteria and propose two methods to apply the defined dispatching criteria sequentially and simultaneously (i.e. fixed dispatching architecture). However the fixed type methods cannot apply the criteria adaptively by considering changes in the semiconductor fabrication factories. To overcome this type of weakness, an adaptive dispatching architecture is proposed for applying the dispatching criteria dynamically based on the factory status. The status can be determined by combining evaluation results from the following three status criteria; target movement, workload balance, and utilization rate. Results from the shop floor in past few periods showed that the proposed methodology gives a good performance with respect to the productivity, workload balance, and machine utilization. We can expect that the proposed adaptive dispatching architecture will be used as a useful tool for operating semiconductor fabrication factories more efficiently and effectively.