• 한국마이크로전자및패키징학회:학술대회논문집
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• 한국마이크로전자및패키징학회 1999년도 1st Korea-Japan Advanced Semiconductor Packaging Technology Seminar
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• pp.45-61
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• 1999

General trend in electronics industry towards multimedia in the 21 century is presented here. All equipments require fast graphic processing together with thin and lightweight assembly technology. In Japan, CSP was developed and applied to mobile equipments for several years, and recently stacked die assembly technology is being developed. In addition, so-called flip chip technology is also being developed and which is applied to MCP and MCM little by little these days. Here current packaging technology in Japan is presented including above.

• 반도체디스플레이기술학회지
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• 제18권4호
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• pp.69-74
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• 2019

The aim of this work is to investigate the effect of the microtip length in a slot-die head on coating of a fine poly(3,4-ethylenedioxythiophene):poly(4-styrenesulfonate) (PEDOT:PSS) stripe. To this end, we have employed a meniscus guide with a 150-㎛-wide microtip and performed roll-to-roll slot-die coatings by varying its length between 500 ㎛ and 50 ㎛. When the microtip length is 150 ㎛ or shorter, we have observed three unexpected phenomena; 1) though the solution spreads much wider than the microtip width, yet the coated stripe width is almost the same as the microtip width, 2) the stripe width decreases, but the stripe thickness is rather increased with increasing coating speed at a fixed flow rate, 3) we obtain stripes much narrower than the microtip width at high coating speeds. It is due to the fact that 1) the meniscus is not well controlled by a short microtip, 2) the main stream of solution from the outlet is very close to the substrate and thus the distributed solution along the head lip merges with the main stream, and 3) the solution is not spread over the entire microtip end at high coating speeds, causing a tiny wobble in the meniscus. Using the 150-㎛-wide and 250-㎛-long microtip, we have fabricated 153-㎛-wide and 94-nm-thick PEDOT:PSS stripe at the maximum coating speed of 13 mm/s. To demonstrate its applicability in solution-processable organic light-emitting diodes (OLEDs), we have also fabricated an OLED device with the fine PEDOT:PSS stripe and obtained strong light emission from it.

• 반도체디스플레이기술학회지
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• 제20권1호
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• pp.70-76
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• 2021

A cylindrical microlens (CML) has been widely used as an optical element for organic light-emitting diodes (OLEDs), light diffusers, image sensors, 3D imaging, etc. To fabricate high-performance optoelectronic devices, the CML with high aspect ratio is demanded. In this work, we report on facile solution-based processes (i.e., slot-die and needle coatings) to fabricate the CML using poly(methyl methacrylate) (PMMA). It is found that compared with needle coating, slot-die coating provides the CML with lower aspect ratio due to the wide spread of solution along the hydrophilic head lip. Although needle coating provides the CML with high aspect ratio, it requires a high precision needle array module. To demonstrate that the aspect ratio of CML can be enhanced using slot-die coating, we have varied the molecular weight of PMMA. We can achieve the CML with higher aspect ratio using PMMA with lower molecular weight at a fixed viscosity because of the higher concentration of PMMA solute in the solution. We have also shown that the aspect ratio of CML can be further boosted by coating it repeatedly. With this scheme, we have fabricated the CML with the width of 252 ㎛ and the thickness of 5.95 ㎛ (aspect ratio=0.024). To visualize its light diffusion property, we have irradiated a laser beam to the CML and observed that the laser beam spreads widely in the vertical direction of the CML.

• 반도체디스플레이기술학회지
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• 제22권4호
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• pp.32-37
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• 2023

For the potential applications in large-area OLED lightings, hydrogen fuel cells, and secondary batteries, we have performed an intermittent coating of high-viscosity polydimethylsiloxane using roll-to-roll slot die coater. During intermittent coating, dead zones inevitably appear where the thickness of PDMS patch films becomes non-uniform, especially at the leading/trailing edge. To reduce it, we have coated the PDMS patches by varying the process parameters such as the installation angle of the slot die head, coating speed, and patch interval. It is observed that the PDMS solution flows down and thus the thickness profile is non-uniform for horizonal intermittent coating, whereas the PDMS solution remaining on the head lip causes an increase in the PDMS thickness at the leading/trailing edges for vertical intermittent coating when the coating velocity is low. As the coating speed increases, however, the dead zone is shown to be reduced. It is addressed that the overall dead zone (the dead zone at the leading edge + the dead zone at the trailing edge) is smaller with horizontal intermittent coating than with vertical intermittent coating.

• 대한금속재료학회지
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• 제48권4호
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• pp.363-368
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• 2010

N,N'-diphenyl-N,N'-bis(3-methylphenyl)1-1' biphenyl-4,4'-diamine (TPD) hole-transporting layers were deposited using a continuous slot-die coating method on ITO/PET flexible substrates. It is crucial that the substrates have a very smooth surface with a RMS roughness of less than 2 nm for the deposition of semiconductor nanocrystals or Quantum Dots. The parameters of the slot-die coating, including the solution concentration of the TPD, the gap between the slot-die and the substrates, and the coating speed were controlled in these experiments. To obtain full coverage of the TPD films on the ITO/PET substrates (40 mm wide and several meters long), the injection rates of the TPD solution were increased proportional to the coating speed of the flexible substrates. Additionally, the injection rates must be increased as the gap distance changes from 400 to 600 ${\mu}m$ at the same coating speed. A RMS surface roughness of less than 2 nm was obtained, in contrast to bare ITO/PET substrates, at 13 nm, as the coating speed and gap distance increased.

• 대한전자공학회논문지SD
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• 제48권7호
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• pp.30-36
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• 2011

많은 반도체 회사들이 메모리 층 사이에서 수직 버스의 역할을 하는 TSV를 사용한 3차원 메모리를 개발하고 있다. 3차원 메모리는 KGD로 이루어지며, 만약 추가 고장이 접합 공정 중에 발생한다면, 반드시 수리되어야 한다. 공유 예비 셀을 가지는 3차원 메모리의 수율을 증진시키기 위해서, 3차원 메모리 내의 메모리 다이를 효과적으로 적층하는 다이 매칭 방법이 필요하다. 본 논문에서는 공유 예비 셀을 가지는 3차원 메모리의 수율 증진을 위해 접합 공정에서 추가 고장이 발생하는 경우를 고려한 다이 매칭 방법을 제안한다. 세 가지 경계 제한 조건이 제안하는 다이 매칭 방법에서 사용된다. 이 조건은 3차원 메모리를 제작하기 위해 선택하는 메모리 다이의 검색 범위를 제한한다. 시뮬레이션 결과는 제안하는 다이 매칭 방법이 3차원 메모리의 수율을 크게 향상 시킬 수 있음을 보여 준다.

• 한국시뮬레이션학회논문지
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• 제19권1호
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• pp.1-11
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• 2010

K 회사는 국내외 반도체 제조업체의 주문에 의해 반도체 패키지 제품을 생산 공급하는 기업이다. 생산 공정은 Die Sawing, 조립, 테스트로 구성된 기계중심의 조립라인 형태를 따르고 있다. 본 논문은 K 회사의 공정분석을 토대로 패키지 공정의 생산량을 늘리기 위한 3가지 방안을 제안하고, 이들을 실제 자료를 이용한 시뮬레이션 모델을 통해 평가하는 사례연구를 다룬다. 3가지 방안은 병목공정에 기계 추가에 의한 라인균형, 제품의 그룹 스케쥴링, 비병목공정에서 작업자의 재배치이다. 시뮬레이션 평가결과, 3가지 방안을 혼합 적용하는 경우에 2.8%의 납기위반율 감소 효과와 함께 17.3%의 가장 높은 일일 생산량 증가를 보여 주는 것으로 나타났다. 3가지 방안의 혼합 적용하는 경우의 투자회수기간은 1.37년으로 매우 짧게 구해졌다.

• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 2013년도 춘계학술대회 논문집
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• pp.657-658
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• 2013

• Design & Manufacturing
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• 제10권3호
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• pp.1-7
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• 2016

In the semiconductor industry the memory and chip were developed to high density memory and high performance chip, so circuit design was also high integrated and the test bed was needed to be thin and fine pitch socket. LGA(Land Grid Array) IC socket with thin wall thickness was designed to satisfy this requirement. The LGA IC socket plastic part was manufacture by injection molding process, it was needed accuracy, stiffness and suit resin with high flowability. After injection molding process the side gates were needed to remove for further assembly process. ln this study, the cold press cutting process was applied to remove the gates. For design of punch and die, the cold press cutting analysis was implemented by$DEFORM-2D^{TM}$ ln consideration of the simulation results, an adequate punch and die was designed and made for the cutting unit. In order to verify the performance of cutting process, the roughness of cutting section of the part was measured and was satisfied in requirement.

• 마이크로전자및패키징학회지
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• 제23권2호
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• pp.79-84
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• 2016

유연전자소자가 외부힘에 의해 변형될 경우 반도체 다이가 기계적 응력 때문에 변형되거나 파괴되고 이러한 변형이나 파괴는 channel의 전자이동도를 변화시키거나 배선의 저항을 증가시켜 집적회로의 동작 오류를 발생시킨다. 따라서 반도체 집적회로는 굽힘 변형이 발생해도 기계적 응력이 발생하지 않는 중립축에 위치하는 것이 바람직하다. 본 연구에서는 굽힘변형을 하는 flip-chip 접합공정이 적용된 face-down flexible packaging system에서 중립축의 위치와 파괴 모드를 조사하였고 반도체 집적회로와 집중응력이 발생한 곳의 응력을 감소시킬 수 있는 방법을 제시하였다. 이를 위해, 설계인자로 유연기판의 두께 및 소재, 반도체 다이의 두께를 고려하였고 설계인자가 중립축의 위치에 미치는 영향을 조사한 결과 유연기판의 두께가 중립축의 위치를 조절하는데 유용한 설계인자임을 알 수 있었다. 3차원 모델을 이용한 유한요소해석 결과 반도체 다이와 유연기판 사이의 Cu bump 접합부에서 항복응력보다 높은 응력이 인가될 수 있음을 확인하였다. 마지막으로 flexible face-down packaging system에서 반도체 다이와 Cu bump 의 응력을 감소시킬 수 있는 설계 방법을 제안하였다.