• 전력전자학회:학술대회논문집
• /
• 전력전자학회 2003년도 춘계전력전자학술대회 논문집(1)
• /
• pp.260-263
• /
• 2003

When ICP(Inductive Coupled Plasma type etching and wafer manufacturing is being processed in semiconductor process, a noxious gas in PFC and CFC system is generated. Gas cleaning dry scrubber is to remove this noxious gas. This paper describes a power source device, 2MHz switching frequency class 2kW RF Generator, used as a main power source of the gas cleaning dry scrubber. The power stage of DC/DC converter is consist of full bridge type converter with 100kHz switching frequency Power amplifier is push pull type inverter with 2MHz switching frequency, and transmission line transformer. The adequacy of the circuit type and the reliability of generating plasma in various load conditions are verified through 50$\Omega$ dummy load and chamber experiments result.

• 한국재료학회지
• /
• 제5권4호
• /
• pp.397-404
• /
• 1995

반도체 세정공정에서 염기성 세정액(SCI, Standard cleaning 1, $NH_{4}$OH + $H_{2}$O_{2}$ + $H_{2}$O)은 공정상 발생되는 여러 오염물 중 파티클의 제거를 위해 널리 사용되고 있는데, SCI 조성중 $NH_{4}$OH양에 따라 세정 중 실리콘의 식각속도를 증가시킨다. 이 연구에서는 SCI 세정이 CZ(Czochralski)와 에피 실리콘 기판 표면에 미치는 영향을 단순세정과 연속적인 산화-HF 식각-SCI 세정공정을 통해 관찰되었다. CZ와 에피 기판을 8$0^{\circ}C$의 1 : 2 : 10과 1 : 1 : 5 SCI 용액에서 60분까지 단순 세정을 했을 때 laser particle scanner와 KLA사의 웨이퍼 검색장치로 측정된 결함의 수는 세정시간에 따라 변화를 보이지 않았다. 그러나 CZ와 에피 기판을 10분간 SCI 세정후 90$0^{\circ}C$에서 산화 HF식각공정을 4번까지 반복하였을 때 에피 기판 표면의 결함수는 감소하는 반면에 CZ기판에서는 직선적으로 증가하였다. 반복적인 산화-HF 식각-XCI 세정공정을 통해 생성된 CZ기판 표면의 결함은 크기가 0.7$\mu$m 이하의 pit과 같은 형상을 보여주었다. 이들 결함은 열처리 중 CZ 기판내와 표면에 산화 석출물들이 형성, 반복적인 HF 식각-SCI 세정공정을 통해 다른 부위에 비해 식각이 빨리 일어나 표면에 생성되는 것으로 여기어 진다.

• 한국산업보건학회지
• /
• 제26권3호
• /
• pp.301-306
• /
• 2016

Objectives: Direct-reading instrument(Photoionization detectors, PID) and quantitative analysis using active type air sampling (Gas chromatography-flame ionization detector, GC-FID) were tested to evaluate their ability to detect volatile organic compounds(VOCs) in a semiconductor manufacturing plant. Methods: The organic compounds used were acetone and ethanol which are normally used as cleaning solutions in the semiconductor manufacturing. The evaluation was based on the preparation of test solutions of known acetone and ethanol concentration in a chamber($600{\times}600{\times}1150mm$). Samples were prepared that would be equivalent to 5~100 ppm for acetone and 10~ 200 ppm ethanol. GC-FID and PID were evaluated simultaneously. Quantitative analysis was performed after sampling and the direct-reading instrument was checked using real-time data logging. Results: Positive correlations between PID and GC-FID were found for acetone and ethanol at 0.04~2.4% for acetone(TLV: 500 ppm) and 0.1~8.3% for ethanol(TLV: 1000 ppm). When the sampling time was 15 min, concentration of test solution was the most similar between measurement methods. However, the longer the sampling time, the less similar the results. PID and GC-FID had similar exposure patterns. Conclusions: The results indicate that PID and GC-FID have similar exposure pattern and positive correlation for detection of acetone and ethanol. Therefore, PID can be used for exposure monitoring for VOCs in the semiconductor manufacturing industry. This study has significance in that it validates measuring occupational exposure using a portable device.

• 반도체디스플레이기술학회지
• /
• 제12권3호
• /
• pp.19-22
• /
• 2013

The purpose of this study is to develop a system that can monitor the amounts of energy consumption during CVD and etching process for semiconductor manufacturing. Specifically, this system is designed to measure the $CO_2$ emission amounts quantitatively by measuring the flow rate of gas used and amount of power consumed during the processes. The processes of CVD equipment can be classified generally into processing step and cleaning step and all the two steps were monitored. In CVD and etcher equipments, various gases including Ar and $O_2$ are used, but Ar, $O_2$ and He were monitored with the use of the LCI data of Korea Environmental Industry & Technology Institute and carbon emission coefficients of EcoInvent. As a result, it was found that the carbon emission amounts of CVD equipment for Ar, $O_2$ and He were $0.030kgCO_2/min$, $4.580{\times}10^{-3}kgCO_2/min$ and $6.817{\times}10^{-4}kgCO_2/min$, respectively and those of etcher equipment for Ar and $O_2$ are $5.111{\times}10^{-3}kgCO_2/min$ and $7.172kgCO_2/min$, respectively.

• 한국산학기술학회논문지
• /
• 제16권8호
• /
• pp.5541-5549
• /
• 2015

본 논문은 반도체 웨이퍼 공정 배기가스 수분제어장치에 적용하기 위하여 인덕션 히터를 사용해서 안전하고 효율적인 전력을 사용하는 히터에 대한 설계방법을 제안한다. 수분을 제거하기 위해서 질소 가스의 흡열 반응을 발생하는 필라멘트 히터를 이용하여 배기가스 제거 시스템이 만들어진다. 이론적인 최적화와 전기적인 구현을 통해서 인덕션 이론은 반도체 웨이퍼 공정 배기가스 시스템을 위한 인덕션 히터 설계과정에 적용되어진다. 제안한 인덕션 히터 설계는 에너지 측면에서 비효율적이고 신뢰성이 떨어지며 안전하지 못한 현재의 설계문제에 대한 해결책을 제시한다. 인덕션 히터의 강인성과 미세조정 설계기법이 질소 히터의 사양내에서 에너지 소모를 최적화한다. 최적화는 배기 파이프의 공진주파수에 의해서 특성화된 ZVS(Zero Voltage Switching)를 기초로 이루어진다. 시스템에서 끼어진 고장 안전(fail-safe) 에너지 리미터는 MOSFET의 궤환 제어를 통하여 전압 레귤레이터를 사용하고 N2 히터 유닛의 사양이내에서 작동하기 위한 성능을 만족하도록 한다. 수치 해석과 설계의 우수성을 위한 기존의 필라멘트 히터와 미세조정한 인덕션 히터 설계의 사양과 성능비교는 제안한 인덕션 히터 설계방법이 우수함을 보여준다.

• 반도체디스플레이기술학회지
• /
• 제16권3호
• /
• pp.47-52
• /
• 2017

Solar cell industry requires high technologies to stabilize apparatuses for the wafer manufacturing. Vibrations of squaring & grinding machines are one of the most critical factors for causing residual stresses of ingots, which are the main reasons of the breakage in the following processes such as wire sawing, cleaning, and modularity. In this study, the structure of a squaring & grinding machine has been analyzed through experiments and computer simulations to figure out the ways to suppress the vibrations effectively, and further to minimize the breakage of wafers. The result shows that simple design changes of applying a few ribs can improve the stability of the machine.

• 반도체디스플레이기술학회지
• /
• 제16권3호
• /
• pp.41-46
• /
• 2017

This study aims to select suitable co-solvents and to obtain optimal process conditions in order to improve process efficiency and productivity through experimental results obtained under various experimental conditions for the etching and rinsing process using liquid carbon dioxide and supercritical carbon dioxide. Acetone was confirmed to be effective through basic experiments and used as the etching solution for MEMS-wafer etching in this study. In the case of using liquid carbon dioxide as the solvent and acetone as the etching solution, these two components were not mixed well and showed a phase separation. Liquid carbon dioxide in the lower layer interfered with contact between acetone and Mems-wafer during etching, and the results after rinsing and drying were not good. Based on the results obtained under various experimental conditions, the optimum process for treating MEMS-wafer using supercritical CO2 as the solvent, acetone as the etching solution, and methanol as the rinsing solution was set up, and MEMS-wafer without stiction can be obtained by continuous etching, rinsing and drying process. In addition, the amount of the etching solution (acetone) and the cleaning liquid (methanol) compared to the initial experimental values can be greatly reduced through optimization of process conditions.

• 미래기술융합논문지
• /
• 제2권4호
• /
• pp.1-6
• /
• 2023

파워인덕터 생산용 표면 UV 인쇄장치 성능 연구는 원기둥 자석의 자력 형성이 상, 하로 형성되게 제작함으로써 제품 고정 시 제품이 뒤집히거나, 세워지는 현상을 방지하는 기술을 적용하여 인쇄 진행 시 품질 소모성 자재(제판, Squeegee)의 파손을 방지하고, 인쇄 품질을 향상시킬 수 있다. 자력의 방향을 바꾼 원기둥 자석의 개발로 파우더 압축으로 제작한 메탈 소재 제품에 대한 고정 방법이 안정화 되어 소형 제품에 대한 생산 능력이 증대할 것이다. 최종적으로 원기둥 자석을 활용한 파워인덕터 표면 UV 인쇄 장치를 연구함으로써, 기존 작업 진행하던 스프레이, Deeping 방식과 차별성을 둘 수 있고, 생산량이 크게 향상될 것이며 결과적으로는 인원 감축으로 원가절감 및 경쟁력 있는 제품 생산을 할 수 있을 것이다.

• 한국세라믹학회지
• /
• 제54권1호
• /
• pp.66-69
• /
• 2017

In this study, the fabrication and electrical properties of aligned single-walled carbon nanotube (SWCNT) networks using a template-based fluidic assembly process are presented. This complementary metal-oxide-semiconductor (CMOS)-friendly process allows the formation of highly aligned lateral nanotube networks on $SiO_2/Si$ substrates, which can be easily integrated onto existing Si-based structures. To measure outstanding electrical properties of organized SWCNT devices, interfacial contact resistance between organized SWCNT devices and Ti/Au electrodes needs to be improved since conventional lithographic cleaning procedures are insufficient for the complete removal of lithographic residues in SWCNT network devices. Using optimized purification steps and controlled developing time, the interfacial contact resistance between SWCNTs and contact electrodes of Ti/Au is reached below 2% of the overall resistance in two-probe SWCNT platform. This structure can withstand current densities ${\sim}10^7A{\cdot}cm^{-2}$, equivalent to copper at similar dimensions. Also failure current density improves with decreasing network width.

• 한국정밀공학회:학술대회논문집
• /
• 한국정밀공학회 1997년도 춘계학술대회 논문집
• /
• pp.921-926
• /
• 1997

SOI(Silicon On lnsulator) technology is many advantages in the gabrication of MOS(Metal-Oxide Semiconductor) and CMOS(Complementary MOS) structures. These include high speed, lower dynamic power consumption,greater packing density, increased radiation tolearence et al. In smiple form of bonded SOL wafer manufacturing, creation of a bonded SOI structure involves oxidizing at least one of the mirror polished silicon surfaces, cleaning the oxidized surface and the surface of the layer to which it will be bonded,bringing the two cleanded surfaces together in close physical proximity, allowing the subsequent room temperature bonding to proceed to completion, and than following this room temperature joining with some form of heat treatment step,and device wafer is thinned to the target thickness. This paper has been performed to investigate the possibility of the bonded SOI wafer manufacturing Especially, we focused on the bonding quality and thinning method. Finally,we achieved the bonded SOI wafer that Si layer thickness is below 3 .mu. m and average roughness is below 5.angs.