• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.11a
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• pp.95-95
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• 2008

본 연구에서는 SiGe p-MOSFET을 제작하여 I-V 특성과 게이트 길이, $V_D$, $V_G$의 변화에 따른 저주파 노이즈특성을 측정하였다. Si 기판위에 성장한 $Si_{0.88}Ge_{0.12}$으로 제작된 SiGe p-MOSFET의 채널은 게이트 산화막과 20nm 정도의 Si Spacer 층으로 분리되어 있다. 게이트 산화막은 열산화에 의해 70$\AA$으로 성장되었고, 게이트 폭은 $25{\mu}m$, 게이트와 소스/드레인 사이의 거리는 2.5때로 제작되었다. 제작된 SiGe p-MOSFET은 빠른 동작 특성, 선형성, 저주파 노이즈 특성이 우수하였다. 제작된 SiGe p-MOSFET의 ESD 에 대한 소자의 신뢰성과 내성을 연구하기 위하여 SiGe P-MOSFET에 ESD를 lkV에서 8kV까지 lkV 간격으로 가한 후, SiGe P-MOSFET의 I-V 특성과 게이트 길이, $V_D$, $V_G$의 변화에 따른 저주파 노이즈특성 변화를 분석 비교하였다.

• JSTS:Journal of Semiconductor Technology and Science
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• v.5 no.2
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• pp.120-126
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• 2005

We have proposed a characteristic method to estimate real composition when multi component oxide films are deposited by ALD. Final atomic concentration ratio was theoretically calculated from the film densities and growth rates for $HfO_2$ and $Al_2O_3$ using ALD processed HfxAhOz mms.W e have transformed initial source feeding ratio during deposition to fins] atomic ratio in $Hf_xAl_yO_z$ films through thickness factors ($R_{HFO_2}$ ami $R_{Al_2O_3}$) ami concentration factor(C) defined in our experiments. Initial source feeding ratio could be transformed into the thickness ratio by each thickness factor. Final atomic ratio was calculated from thickness ratio by concentration factor. It has been successfully confirmed that the predicted atomic ratio was in good agreement with the actual measured value by ICP-MS analysis.

• Proceedings of the KIEE Conference
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• 1995.11a
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• pp.603-605
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• 1995

We present a novel method. to fabricate surface micromachined structures without their sticking on the substrate. An anhydrous HF/$CH_3OH$ vapor-phase etching (VPE) of sacrificial $SiO_2$ layers was employed to release 0.5-2 {\mu}m$ thick polysilicon cantilevers. The fabricated structures were observed using scanning electron microscope and 3-dimensional optical microscope. The results show that we can successfully make cantilever beams up to 1200{\mu}m$ long without sticking. Annealing effects on residual stress of polysilicon microstructures were also investigated. Anneal ins at 1100$^{\circ}C$ for 1 hour was found to be effective to release the residual stress of the polysilicon microstructures. These VPE and anneal ins techniques will be useful in surface micromachining technologies.

• JSTS:Journal of Semiconductor Technology and Science
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• v.5 no.4
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• pp.221-228
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• 2005

In this work, our goal is to develop a fast and accurate power model of the ARM926EJ-S processor in the industrial design environment. Compared with existing work on processor power modeling which focuses on the power states of processor core, our model mostly focuses on the cache power model. It gives more than 93% accuracy and 1600 times speedup compared with post-layout gate-level power estimation. We also address two practical issues in applying the processor power model to the real design environment. One is to incorporate the power model into an existing commercial instruction set simulator. The other is the re-characterization of power model parameters to cope with different gate-level netlists of the processor obtained from different design teams and different fabrication technology.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.475-476
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• 2006

Recently, the demand for high density MOSFET arrays are increasing. In implementing 3-D devices to this end, it is inevitable to ion-implant vertically in order to avoid screening effects caused by high silicon fins. In this study, the dependency of drain current characteristics on doping profiles is investigated by 3-D numerical analysis. The position of concentration peak (PCP) and the doping gradient are varied to look into the effects on primary current characteristics. Through these analyses, criteria of ion-implantation for 3-D devices are established.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.28 no.4
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• pp.218-221
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• 2015

Power MOSFETs (metal oxide semiconductor field effect transistor) operate as energy control semiconductor switches. In order to reduce energy loss of the device during switch-on state, it is essential to increase its conductance. In this study we have investigated a structure to reduce the on-resistance characteristics of the MOSFET. We have a proposed MOSFET structure of active cells region buried under the gate pad. The measurement are carried out with a EDS to analyze electrical characteristics, and the proposed MOSFET are compared with the conventional MOSFET. The result of proposed MOSFET was 1.68[${\Omega}$], showing 10% improvement compared to the conventional MOSFET at 700[V].

• Journal of the Ergonomics Society of Korea
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• v.30 no.1
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• pp.117-125
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• 2011

While human error happens repeatedly in the semiconductor industry in Korea, which has brought a tremendous loss from manpower, welfare etc., there are limitations to human error prevention activities. When a semiconductor company introduces new machines and facilities from Japan or Germany, the companies often do not consider human factors in the design. Also, semiconductor companies are so occupied with promoting increased productivity, their attention to human errors has been pushed aside. Negative aspects of technical exchange associated with safety management are one aspect of the industry's nature. A semiconductor company recently began acknowledging on the back of TQM(Total Quality Management) that human error has a decisive effect on the safety. There are a number of uncontrollable and hard to handle event sets because the nature of these events with a human error may often be threatened or very intensive. It is strongly required that systemic studies should be performed to grasp the whole picture of a current situation for hazard factors. This study aims to examine the human error approach through the case of human error prevention field activities in a semiconductor industry compared with the activities and experience in nuclear power plants.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2007.06a
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• pp.187-187
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• 2007

This paper presents the electrical properties of SiGe HBTs designed with bottom collector and single metal layer structure for RF power amplifier. Base layer was formed with graded-SiGe/Si structures and the collector place to the bottom of the device. Bottom collector and single metal layer structures could significantly simplify the fabrication process. We studied about the influence of SiGe base thickness, number of emitter fingers and temperature dependence (< $200^{\circ}C$) on electrical properties. The feasible application in 1~2GHz frequency from measured data $BV_{CEO}$ ~10V, $f_r$~14 GHz, ${\beta\simeq}110$, NF~1 dB using packaged SiGe HBTs. We will discuss the temperature dependent current flow through the e-b, b-c junctions to understand stability and performance of the device.

• Transactions on Electrical and Electronic Materials
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• v.11 no.1
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• pp.24-28
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• 2010

A simulation study of a current-mode direct current (DC)-DC buck converter is presented in this paper. The converter, with a fully integrated power module, is implemented by using sense method metal-oxide-semiconductor field-effect transistor (MOSFET) and bipolar complementary metal-oxide-semiconductor (BiCMOS) technology. When the MOSFET is used in a current sensor, the sensed inductor current with an internal ramp signal can be used for feedback control. In addition, the BiCMOS technology is applied in the converter for an accurate current sensing and a low power consumption. The DC-DC converter is designed using the standard $0.35\;{\mu}m$ CMOS process. An off-chip LC filter is designed with an inductance of 1 mH and a capacitance of 12.5 nF. The simulation results show that the error between the sensing signal and the inductor current can be controlled to be within 3%. The characteristics of the error amplification and output ripple are much improved, as compared to converters using conventional CMOS circuits.

• Journal of Korean Society of Occupational and Environmental Hygiene
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• v.32 no.2
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• pp.111-115
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• 2022

Objectives: The purpose of this study is to verify whether droplet-induced propagation, the main route of infectious diseases such as COVID-19, can occur in semiconductor FAB (Fabrication), based on research results on general droplet propagation. Methods: Through data surveys droplet propagation was modeled through simulation and experimental case analysis according to general (without mask) and mask-wearing conditions, and the risk of droplet propagation was inferred by reflecting semiconductor FAB operation conditions (air current, air conditioning system, humidity, filter conditions). Results: Based on the results investigated to predict the possibility of spreading infectious diseases in semiconductor FAB, the total amount of droplet propagation (concentration), propagation distance, and virus life in FAB were inferred by reflecting the management parameter of semiconductor FAB. Conclusions: The total amount(concentration) of droplet propagation in the semiconductor fab is most affected by the presence or absence of wearing a mask and the line air dilution rate has some influence. when worn it spreads within 0.35~1m, and since the humidity is constant the virus can survive in the air for up to 3 hours. as a result the semiconductor fab is judged to be and effective space to block virus propagation due to the special environmental condition of a clean room.