JSTS:Journal of Semiconductor Technology and Science

The Institute of Electronics and Information Engineers (대한전자공학회)
권호 표지

An Industrial Case Study of the ARM926EJ-S Power Modeling

  • Kim, Hyun-Suk (CAE center, System LSI division, Semiconductor Business, Samsung Electronics, Co. Ltd.) ;
  • Kim, Seok-Hoon (CAE center, System LSI division, Semiconductor Business, Samsung Electronics, Co. Ltd.) ;
  • Lee, Ik-Hwan (CAE center, System LSI division, Semiconductor Business, Samsung Electronics, Co. Ltd.) ;
  • Yoo, Sung-Joo (CAE center, System LSI division, Semiconductor Business, Samsung Electronics, Co. Ltd.) ;
  • Chung, Eui-Young (School of Electrical and Electronic Engineering, Yeonsei University) ;
  • Choi, Kyu-Myung (CAE center, System LSI division, Semiconductor Business, Samsung Electronics, Co. Ltd.) ;
  • Kong, Jeong-Taek (CAE center, System LSI division, Semiconductor Business, Samsung Electronics, Co. Ltd.) ;
  • Eo, Soo-Kwan (CAE center, System LSI division, Semiconductor Business, Samsung Electronics, Co. Ltd.)
  • Published : 2005.12.31
Download PDF
⟨ Previous Next ⟩

Abstract

In this work, our goal is to develop a fast and accurate power model of the ARM926EJ-S processor in the industrial design environment. Compared with existing work on processor power modeling which focuses on the power states of processor core, our model mostly focuses on the cache power model. It gives more than 93% accuracy and 1600 times speedup compared with post-layout gate-level power estimation. We also address two practical issues in applying the processor power model to the real design environment. One is to incorporate the power model into an existing commercial instruction set simulator. The other is the re-characterization of power model parameters to cope with different gate-level netlists of the processor obtained from different design teams and different fabrication technology.

Keywords

References

  1. MEDEA+ EDA Roamap, 2003. http://www.medeaplus.org
  2. International Technology Roadmap for Semiconductor (ITRS), http://public.itrs.net/Files/2003ITRS/Home2003.htm
  3. ISO/IEC 14496-10 and ITU-T Rec. H.264, Advanced Video Coding, 2003
  4. D. Brooks, V. Tiwari, and M. Martonosi, 'Wattch: a framework for architectural-level power analysis and optimizations,' in ISCA'00, pp. 83-94, 2000
  5. W. Ye, N. Vijaykrishnan, M. Kandemir, and M. J.Irwin, 'The design and use of simplepower: a cycleaccurate energy estimation tool,' in DAC'00, pp. 340-345, 2000
  6. V. Tiwari, S. Malik, and A. Wolfe, 'Power analysis of embedded software:a first step towards software power minimization,' IEEE Trans. on VLSI systems, pp. 437-445, December 1994 https://doi.org/10.1109/92.335012
  7. G. Gontreras, M. Martonosi, J. Peng, R. Ju, and G.-Y. Lueh, 'XTREM: a power simulator for the Intel XScale core,' in LCTES'04, pp. 115-125, 2004 https://doi.org/10.1145/997163.997180
  8. A. Sama, M. Balakrishnan, and J. F. M. Theeuwen, 'Speeding up Power Estimation of Embedded Software.' in ISLPED'00, pp. 191-196, 2000 https://doi.org/10.1145/344166.344580
  9. A. Sinha, and A. Chandrakasan, 'JouleTrack: a web based tool for software energy profiling,' in DAC'01, pp. 220-225, 2001 https://doi.org/10.1145/378239.378467
  10. M. Lee, et al., 'Power Analysis and Low-Power Scheduling Techniques for Embedded DSP Software,' In Proc. ISSS, 1995 https://doi.org/10.1109/ISSS.1995.520621
  11. J. Seo, et al., 'Profile-based Optimal Intra-task Voltage Scheduling for Hard Real-Time Applications,' in Proc. DAC, 2005 https://doi.org/10.1145/996566.996597
  12. DTSE Methodology, http://www.imec.be/design/dtse/methodology.shtml