• Proceedings of the Korean Vacuum Society Conference
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• 2011.02a
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• pp.188-188
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• 2011

Recently, scaling down of ULSI (Ultra Large Scale Integration) circuit of CMOS (Complementary Meta Oxide Semiconductor) based electronic devices, the electronic devices, become much faster and smaller size that are promising property of semiconductor market. However, very narrow interconnect line width has some disadvantages. Deposition of conformal and thin barrier is not easy. And metallization process needs deposition of diffusion barrier and glue layer for EP/ELP deposition. Thus, there is not enough space for copper filling process. In order to get over these negative effects, simple process of copper metallization is important. In this study, Cu-V alloy layer was deposited using of DC/RF magnetron sputter deposition system. Cu-V alloy film was deposited on the plane SiO2/Si bi-layer substrate with smooth surface. Cu-V film's thickness was about 50 nm. Cu-V alloy film deposited at $150^{\circ}C$. XRD, AFM, Hall measurement system, and AES were used to analyze this work. For the barrier formation, annealing temperature was 300, 400, $500^{\circ}C$ (1 hour). Barrier thermal stability was tested by I-V(leakage current) and XRD analysis after 300, 500, $700^{\circ}C$ (12 hour) annealing. With this research, over $500^{\circ}C$ annealed barrier has large leakage current. However vanadium-based diffusion barrier annealed at $400^{\circ}C$ has good thermal stability. Therefore thermal stability of vanadium-based diffusion barrier is desirable for copper interconnection.

• Korean Journal of Materials Research
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• v.12 no.9
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• pp.696-700
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• 2002

The Ti-aluminide intermetallic compound was formed from high purity elemental Ti and Al foils by self-propagating, high-temperature synthesis(SHS) in hot press. formation of $TiAl_3$ at the interface between Ti and Al foils was controlled by temperature, pressure, heating rate, and so on. According to the thermal analysis, it is known in this study that the heating rate is the most important factor to form the intermetallic compound by this SHS reaction. The V layer addition between Al and Ti foils increased SHS reaction temperatures. The fully dense, well-boned inter-metallic composite($TiA1/Ti_3$Al) sheets of 700 m thickness were formed by heat treatment at $1000^{\circ}C$ for 10 hours after the SHS reaction of alternatively layered 10 Ti and 9 Al foils with the V coating layer. The phases and microstructures of intermetallic composite sheets were confirmed by EPMA and XRD.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.30 no.10
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• pp.631-636
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• 2017

The degradation mechanism of $Mo_xW_{1-x}Si_2$ ultrahigh-temperature heating elements fabricated by self-propagating high-temperature synthesiswas investigated. The $Mo_xW_{1-x}Si_2$ specimens (with and without post-annealing) were subjected to ADTs (accelerated degradation tests) at temperatures up to $1,700^{\circ}C$ at heating rates of 3, 4, 5, 7, and $14^{\circ}C/min$. The surface loads of all the specimen heaters were increased with the increase in the target temperature. For the $Mo_xW_{1-x}Si_2$ specimens without annealing, many pores and secondary-phase particles were observed in the microstructure; the surface load increased to $23.9W/cm^2$ at $1,700^{\circ}C$, while the bending strength drastically reduced to 242 MPa. In contrast, the $Mo_xW_{1-x}Si_2$ specimens after post-annealing retained $single-Mo_xW_{1-x}Si_2$ phases and showed superior durability after the ADT. Consequently, it is thought that the formation of microcracks and coarse secondary phases during the ADT are the main causes for the degraded performance of the $Mo_xW_{1-x}Si_2$ heating elements without post-annealing.

• Korean Journal of Materials Research
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• v.6 no.7
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• pp.733-741
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• 1996

In this study MeV Si self ion implantations were done to reveal the intrinsic behavior of defect formation by excluding the possibility of chemical interactions between substrate atoms and dopant ones. Self implantations were conducted using Tandem Accelerator with energy ranges from 1 to 3 MeV. Defect formation by high energy ion implantation has a significant characteristics in that the lattice damage is concentrated near Rp and isolated from the surface. In order to investigate the energy dependence on defect formation, implantation energies were varied from 1 to 3 MeV under a constant dose of $1{\times}10^{15}/cm^2$. RBS channe!ed spectra showed that the depth at which as-implanted damaged layer formed increases as energy increases and that near surface region maintains better crystallinity as energy increases. Cross sectional TEM results agree well with RBS ones. In a TEM image as-implanted damaged layer appears as a dark band, where secondary defects are formed upon annealing. In the case of 2 MeV $Si^+$ self implantation a critical dose for the secondary defect formation was found to be between $3{\times}10^{14}/cm^24$ and $5{\times}10^{14}/cm^2$. Upon annealing the upper layer of the dark band was removed while the bottom part of the dark band did not move. The observed defect behavior by TEM was interpreted by Monte Carlo computer simulations using TRIM-code. SIMS analyses indicated that the secondary defect formed after annealing gettered oxygen impurities existed in silicon.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.29 no.4
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• pp.215-217
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• 2016

For the improvement of the anti-pollution properties of porcelain electrical insulators, in this study, we have applied the functional film to the surface of insulator. The functional films were coated on the ceramic substrates which components were like the porcelain electrical insulator. The coating material was applied to ceramic substrate by spray coating method and then the film was cured at around $300^{\circ}C$ for 10 minutes with different gas ambient, such as $O_2$, $N_2$, and only vacuum. We have measured the contact angle of the coated surface, and obtained the lowest angle ($8.9^{\circ}$) and a strong hydrophilic property at vacuum condition. The anti-pollution properties were measured, revealing that as the contact angle decreased, the anti-pollution properties improved. The mechanical hardness and adhesion were both excellent regardless of the annealing ambient.

• Macromolecular Research
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• v.17 no.3
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• pp.181-186
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• 2009

We fabricated ordered micro/nano patterns induced by controlled dewetting on the topographically patterned PS/P4VP bilayer thin film. The method is based on utilizing microimprinting lithography to induce a topographically heterogeneous bilayer film that allows the controlled dewetting upon subsequent thermal annealing. The dewetting that was initiated strictly at the boundary of the thicker and thinner regions was guided by the presence of the topographic structure. The dewetting front velocity of the microdomains in the confined regions was linearly proportional to the measurement time, which enabled us to control the size of the dewet domain with annealing time. In particular, the submicron sized dot arrays between lines were generated with ease when the dewetting was confined into geometry with a few microns in size. The kinetically driven, non-lithographical pattern structures accompanied the pattern reduction to 400%. The pattern arrays on a transparent glass substrate were especially useful for non-circular microlens arrays where the focal length of the lens was easily tunable by controlling the thermal annealing.

• Proceedings of the Acoustical Society of Korea Conference
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• 1994.06c
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• pp.407-410
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• 1994

In this paper, we describe the new unsuperivised learning algorithm, SASOM. It can solve the defects of the conventional SOM that the state of network can't converge to the minimum point. The proposed algorithm uses the object function which can evaluate the state of network in learning and adjusts the learning rate flexibly according to the evaluation of the object function. We implement the simulated annealing which is applied to the conventional network using the object function and the learning rate. Finally, the proposed algorithm can make the state of network converged to the global minimum. Using the two-dimensional input vectors with uniform distribution, we graphically compared the ordering ability of SOM with that of SASOM. We carried out the recognitioin on the new algorithm for all Korean phonemes and some continuous speech.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.30A no.10
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• pp.41-50
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• 1993

This paper describes the fabrication process and electrical characteristics of PSA (Polysilicon Self-Align) bipolar transistors with a thin base width of 1100.angs.. To realize this shallow junction depth, one-step rapid thermal annealing(RTA) technology has been applied instead of conventional furnace annealing process. It has been shown that the series resistances and parasitic capacitances are significantly reduced in the device with emitter area of 1${\times}4{\mu}m^{2}$. The switching speed of 2.4ns/gate was obtained by measuring the minimum propagation delay time in the I$^{2}$L ring oscillator with 31 stages.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1996.05a
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• pp.264-268
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• 1996

Directional coupling optical switch which on the LiNbO$_3$ substrate is fabricated by using proton exchange method and self-aligned method. Proton exchange of proton diffusion method was applied to pattern a waveguide on LiNbO$_3$ substrate. The annealing at 400[$^{\circ}C$] was caroled out to control waveguide width and depth. The process of proton exchange was done at 150[$^{\circ}C$] for 120[min], 200[$^{\circ}C$] for 60[min] and annealing process was done at 400[$^{\circ}C$] for 90[min], 400[$^{\circ}C$] for 60[min]. The high speed directional coupling optical switch has very good figures of merits:the measured high frequency power were achieved.

• Proceedings of the Materials Research Society of Korea Conference
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• 1993.05a
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• pp.62-63
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• 1993

Salicide(Self-aligned) CoSi$_2$의 형성을 알아보기 위하여, 단결정 실리콘 기판내에 불순물 주입에 따른 실리사이드의 형성영향을 알아보는, As,BF$_2$를 주입 한 시편과, 코발트와 SiO$_2$를 증착한 시편을 준비하였다. RF sputtering 방식으로 각각의 기판위에 코발트를 증착 한 후 Rapid Thermal Annealing(RTA) 온도 400-100$0^{\circ}C$영역에서 20초 동안 열처리 하였다. RTA 온도 80$0^{\circ}C$에서 비저항이 약 18$\mu$$\Omega$-cm정도의 CoSi$_2$를 형성 시켰으며 SEM 과 $\alpha$-step 으로 확인된 Si 기판과 코발트 실리사이드의 계면 roughness 및 surface roughness는 우수하였고, CoSi$_2$의 두께 증가에 따른 실리콘 소모량의 증가에 따라 기판내에 있던 As,BF$_2$ 이온들이 실리사이드내로 재분포 되는 현상을 보였다.CoSi$_2$/Si 계면간의 열적안정성은 $N_2$분위기로 30분간 Furnace Annealing 온도 100$0^{\circ}C$까지 CoSi$_2$의 응집화 현상이 일어나지 않았다.