• Proceedings of the Materials Research Society of Korea Conference
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• 2009.05a
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• pp.22.2-22.2
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• 2009

Currently, metal silicides become increasingly more essential part as a contact material in complimentary metal-oxide-semiconductor (CMOS). Among various silicides, NiSi has several advantages such as low resistivity against narrow line width and low Si consumption. Generally, metal silicides are formed through physical vapor deposition (PVD) of metal film, followed by annealing. Nanoscale devices require formation of contact in the inside of deep contact holes, especially for memory device. However, PVD may suffer from poor conformality in deep contact holes. Therefore, Atomic layer deposition (ALD) can be a promising method since it can produce thin films with excellent conformality and atomic scale thickness controllability through the self-saturated surface reaction. In this study, Ni thin films were deposited by thermal ALD using bis(dimethylamino-2-methyl-2-butoxo)nickel [Ni(dmamb)2] as a precursor and NH3 gas as a reactant. The Ni ALD produced pure metallic Ni films with low resistivity of 25 $\mu{\Omega}cm$. In addition, it showed the excellent conformality in nanoscale contact holes as well as on Si nanowires. Meanwhile, the Ni ALD was applied to area-selective ALD using octadecyltrichlorosilane (OTS) self-assembled monolayer as a blocking layer. Due to the differences of the nucleation on OTS modified surfaces toward ALD reaction, ALD Ni films were selectively deposited on un-coated OTS region, producing 3 ${\mu}m$-width Ni line patterns without expensive patterning process.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.35 no.5
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• pp.439-444
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• 2022

Laser-induced plasmonic sintering of metal nanoparticles (NPs) is a promising technology to fabricate flexible conducting electrodes, since it provides instantaneous, simple, and scalable manufacturing strategies without requiring costly facilities and complex processes. However, the metal NPs are quite expensive because complicated synthesis procedures are needed to achieve long-term reliability with regard to chemical deterioration and NP aggregation. Herein, we report laser-induced Ag NP self-generation and sequential sintering process based on low-cost Ag organometallic material for demonstrating high-quality microelectrodes. Upon the irradiation of laser with 532 nm wavelength, pre-baked Ag organometallic film coated on a transparent polyimide substrate was transformed into a high-performance Ag conductor (resistivity of 2.2 × 10^-4 Ω·cm). To verify the practical usefulness of the technology, we successfully demonstrated a wearable transparent heater by using Ag-mesh transparent electrodes, which exhibited a high transmittance of 80% and low sheet resistance of 7 Ω/square.

• Proceedings of the Korean Vacuum Society Conference
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• 1999.07a
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• pp.162-162
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• 1999

초고주파 집적회로의 핵심소자로 각광을 받고 있는 GaAs MESFET(MEtal-emiconductor)은 게이트 형성 공정이 가장 중요하며, WNx 내화금속을 이용한 planar 게이트 구조의 경우 임계전압(Vth:threshold voltage)의 균일도가 우수할 뿐만 아니라 특히 Side-wall을 이용한 self-align 게이트는 소오스 저항을 줄일 수 있어 고성능의 소자 제작을 가능하게 한다.(1) 본 연구의 핵심이 되는 Side-wall을 형성하기 위하여 PECVD법에 의한 SiOx 박막을 증착하고, 건식식각법을 이용하여 SiOx side-wall을 형성하였다. 이 공정을 이용하여 소오스 저항이 낮고 임계전압의 균일도가 우수한 고성능의 self-aligned gate MESFET을 제작하였다. 3inch GaAs 기판상에 이온주입법에 의한 채널 형성, d.c. 스퍼터링법에 의한 WNx 증착, PECVD법에 의한 SiOx 증착, MERIE(Magnetic Enhanced Reactive Ion Etcing)에 의한 Side-wall 형성, LDD(Lightly Doped Drain)와 N+ 이온주입, 그리고 RTA(Rapid Thermal Annealing)를 사용하여 활성화 공정을 수행하였다. 채널은 40keV, 4312/cm2로, LDD는 50keV, 8e12/cm2로 이온주입하였고, 4000A의 SiOx를 증착한 후 2500A의 Side-wall을 형성하였다. 옴익 접촉은 AuGe/Ni/Au 합금을 이용하였고, 소자의 최종 Passivation은 SiNx 박막을 이용하였다. 제작된 소자의 전기적 특성은 hp4145B parameter analyzer를 이용한 전압-전류 측정을 통하여 평가하였다. Side-wall 형성은 0.3$\mu\textrm{m}$ 이상의 패턴크기에서 수직으로 잘 형성되었고, 본 연궁에서는 게이트 길이가 0.5$\mu\textrm{m}$인 MESFET을 제작하였다. d.c. 특성 측정 결과 Vds=2.0V에서 임계전압은 -0.78V, 트랜스컨덕턴스는 354mS/mm, 그리고 포화전류는 171mA/mm로 평가되었다. 특히 본 연구에서 개발된 트랜지스터의 게이트 전압 변화에 따른 균일한 트랜스 컨덕턴스의 특성은 RF 소자로 사용할 때 마이크로 웨이브의 왜곡특성을 없애주기 때문에 균일한 신호의 전달을 가능하게 한다. 0.5$\mu\textrm{m}$$\times$100$\mu\textrm{m}$ 게이트 MESFET을 이용한 S-parameter 측정과 Curve fitting 으로부터 차단주파수 fT는 40GHz 이상으로 평가되었고, 특히 균일한 트랜스컨덕턴스의 경향과 함께 차단주파수 역시 게이트 바이어스, 즉 소오스-드레스인 전류의 변화에 따라 균일한 값을 보였다. 본 연구에서 개발된 Side-wall 공정은 게이트 길이가 0.3$\mu\textrm{m}$까지 작은 경우에도 사용가능하며, WNx self-align gate MEESFET은 낮은 소오스저항, 균일한 임계전압 특성, 그리고 높고 균일한 트랜스 컨덕턴스 특성으로 HHP(Hend-Held Phone) 및 PCS(Personal communication System)와 같은 이동 통신용 단말기의 MMICs(Monolithic Microwave Integrates Circuits)의 제작에 활용될 것으로 기대된다.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.32A no.11
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• pp.35-43
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• 1995

To obtain high quality of $Ta_{2}O_{5}$ film, two dielectric layers of $Si_{3}N_{4}$ and $Ta_{2}O_{5}$ were subsequently formed on Si wafer. Silicon nitride films were thermally grown in 10 Torr ammonia ambient by R.F induced heating system. The thickness of thermally grown $Si_{3}N_{4}$ film was able to be controlled in the range of tens $\AA$ due to the self-limited growth property. $Ta_{2}O_{5}$ film of 200$\AA$ thickness was then deposited on the as-grown $Si_{3}N_{4}$ film about 25$\AA$ thickness by sputtering method and annealed at $900^{\circ}C$in $O_{2}$ ambient for 1hr. Stoichiometry film was prepared by the annealing in oxygen ambient. Despite the high temperature anneal process, silicon oxide layer was not grown at the interface of the layered films because of the oxidation barrier effect of Si$_{3}$N$_{4}$ film. The fabricated $Ta_{2}O_{5}$/$Si_{3}N_{4}$ film showed low leakage current less than several nA and high dielectric breakdown strength.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.39 no.12
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• pp.1245-1249
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• 2015

This study investigated the reflection spectra of wrinkled metal/polymer multilayers. A wavy surface was self-assembled by annealing an aluminum-coated poly(methyl metacrylate) layer on a silicon substrate. The total and diffuse reflectance characteristics of the sample with additional metal coatings(aluminum or silver) were evaluated in the visible wavelength(400~800 nm) using a spectrophotometer. The results showed that the wrinkled surface enhanced the diffuse reflectance up to 40~50% in the lower-wavelength range, demonstrating its potential for applications to optical thin-film devices.

• Transactions on Electrical and Electronic Materials
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• v.17 no.5
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• pp.302-305
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• 2016

In this paper, a low on-resistance and high current driving capability trench gate power metal-oxide-semiconductor field-effect transistor (MOSFET) incorporating a current sensing feature is proposed and evaluated. In order to realize higher cell density, higher current driving capability, cost-effective production, and higher reliability, self-aligned trench etching and hydrogen annealing techniques are developed. While maintaining low threshold voltage and simultaneously improving gate oxide integrity, the double-layer gate oxide technology was adapted. The trench gate power MOSFET was designed with a 0.6 μm trench width and 3.0 μm cell pitch. The evaluated on-resistance and breakdown voltage of the device were less than 24 mΩ and 105 V, respectively. The measured sensing ratio was approximately 70:1. Sensing ratio variations depending on the gate applied voltage of 4 V ~ 10 V were less than 5.6%.

• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.4
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• pp.454-461
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• 2015

Light enhancement of GaN based light emitting diodes (LEDs) have been investigated by texturing the top p-GaN surface. Nano-textured LEDs have been fabricated using self-assembled Ni nano mask during dry etching process. Experimental results were further compared with simulation data. Three types of LEDs were fabricated: Conventional (planar LED), Surface nano-porous (porous LED) and Surface nano-cluster (cluster LED). Compared to planar LED there were about 100% and 54% enhancement of light output power for porous and cluster LED respectively at an injection current of 20 mA. Moreover, simulation result showed consistency with experimental result. The increased probability of light scattering at the nano-textured GaN-air interface is the major reason for increasing the light extraction efficiency.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.34D no.5
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• pp.32-44
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• 1997

A three-dimensional (3D) full-dynamic damage model for ion implantation in crystalline silicon was proposed to calculate more accurately point defect distributions and ion-implanted concentration profiles during ion implantation process. The developed model was based on the physical monte carlo approach. This model was applied to simulate B and BF2 implantation. We compared our results for damage distributions with those of the analytical kinchin-pease approach. In our result, the point defect distributions obtained by our new model are less than those of kinchin-pease approach, and the vacancy distributions differ from the interstitial distributions. The vacancy concentrations are higher than the interstitial ones before 0.8 . Rp to the silicon surface, and after the 0.8 . Rp to the silicon bulk, the interstitial concentrations are revesrsely higher than the vacancy ones.The fully-dynamic damage model for the accumulative damage during ion implantation follows all of the trajectories of both ions and recoiled silicons and, concurrently, the cumulative damage effect on the ions and the recoiled silicons are considered dynamically by introducing the distributon probability of the point defect. In addition, the self-annealing effect of the vacancy-interstitial recombination during ion implantation at room temperature is considered, which resulted in the saturation level for the damage distribution.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.29A no.2
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• pp.68-76
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• 1992

Concurrent Junction process (simultaneous formation of a silicide and a junction on the implanted substrate) by Rapid Thermal Annealig has been investigated. Electrical and material properties of CoSi$_2$ films were analyzed with Alpha Step, 4-point probe, X-ray diffraction(XRD) and Scanning Electron Microscope(SEM). And CoSi$_2$ junctions were examined with Spreading Resistance probe in order to see the redistribution of electrically activated dopants and determined the junction depth. Two step annealing process, which was 80$0^{\circ}C$ for 30sec and 100$0^{\circ}C$ for 30sec in NS12T ambient was employed to form CoSi$_2$ and shallow junctions. Resistivity of CoSi$_2$ was turned out to be 11-15${\mu}$cm and shallow junctions less than 0.1$\mu$m were successfully formed by the process. It was found that the dopant concentration at CoSi$_2$/Si interface increased as decreasing the thickness of Co films in case of $p^{+}/n$ and $n^{+}/p$ junctions while the junction depth decreased as increasing CoSiS12T thickness in case of $p^{+}/n$ junction.

• Toxicological Research
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• v.26 no.1
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• pp.15-19
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• 2010

Mesenchymal stem cells (MSCs) have greater potential for immediate clinical and toxicological applications, due to their ability to self-renew, proliferate, and differentiate into a variety of cell types. To identify novel candidate genes that were specifically expressed during transdifferentiation of human MSCs to neuronal cells, we performed a differential expression analysis with random priming approach using annealing control primer-based differential display reverse transcription-polymerase chain reaction approach. We identified genes for acyl-CoA thioesterase, tissue inhibitor of metalloproteinases-1, brain glycogen phosphorylase, ubiquitin C-terminal hydrolase and aldehyde reductase were up-regualted, whereas genes for transgelin and heparan sulfate proteoglycan were down-regulated in MSC-derived neurons. These differentially expressed genes may have potential role in regulation of neurogenesis. This study could be applied to environmental toxicology in the field of testing the toxicity of a chemical or a physical agent.