• Proceedings of the Materials Research Society of Korea Conference
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• 2001.05a
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• pp.66-66
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• 2001

• Journal of the Microelectronics and Packaging Society
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• v.25 no.3
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• pp.61-66
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• 2018

This research scrutinizes the self-annealing characteristics of copper used to metal interconnection for application of DRAM fabrication process. As the time goes after the copper deposited, the grain of copper is growing. It is called self-annealing. We use the electroplating method for copper deposition and estimate two kinds of electroplating chemicals having different organic additives. As the time of self-annealing is elapsed, sheet resistance decreases with logarithmic dependence of time and is finally saturated. The improvement of sheet resistance is approximately 20%. The saturation time of experimental sample is shorter than that of reference sample. We can find that self-annealing is highly efficient in grain growth of copper through the measurement of TEM analysis. The structure of copper grain is similar to the bamboo type useful for current flow. The results of thermal excursion characteristics show that the reliability of self-annealed sample is better than that of sample annealed at higher temperature. The self-annealed sample is not contained in hillock. The self-annealed samples grow until $2{\mu}m$ and develop in [100] direction more favorable for reliability.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.20 no.10
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• pp.864-868
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• 2007

Effect of high-temperature annealing on morphology of fully coherent self-assembled InAs quantum dots' grown on Si (100) substrates at $450^{\circ}C$ by atmospheric pressure metalorganic chemical vapor deposition(APMOCVD) was investigated by atomic force microscopy(AFM). When the dots were annealed at 500 - 600$^{\circ}C$ for 15 sec - 60 min, there was no appreciable change in the dot density but the heights of the dots increased along with the reduction in the diameters. In segregation from the InAs quantum dots and/or from the 2-dimensional InAs wetting layer which was not transformed into quantum dots looked responsible for this change in the dot size. However the change rates remained almost same regardless of annealing time and temperature, which may indicate that the morphological change due to thermal annealing is done instantly when the dots are exposed to high temperature annealing.

• Journal of the Korean Society for Precision Engineering
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• v.20 no.1
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• pp.240-247
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• 2003

The tribological characteristics of FDTS (1H, 1H, 2H, 2H-Perflurodecyltrichlorosilane) SAM (self-assembled monolayer) and OTS (octadecyltrichlorosilane) SAM treated by high temperature annealing have been investigated from the viewpoint of stiction, adhesion and friction in micro/nano scale. From the experimental results, it was found that OTS SAM gets destroyed at 20$0^{\circ}C$ and stiction, adhesion and friction coefficient increased, but FDTS SAM was stable up to 40$0^{\circ}C$. Also, it was found that the friction coefficient of normal OTS SAM below 20$0^{\circ}C$ is lower than that of FDTS SAM in micro/nano scale, but stiction and adhesion is vice versa. This work shows the importance of surface group of self-assembled monolayer in dictating the tribological characteristics and thermal stability.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1992.05a
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• pp.54-57
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• 1992

An electro-optical single modulator is fabricated in X-cut LiNbO$_3$by the annealed proton exchange and self-aligned method. First, the effect of annealing is characterized by examining single optical modulator. It is found that by controlling the annealing time, the single optical modulator can be made widely variable. The on-off state of modulator is performed by annealing process and self-aligned electrodes are used in fabricating the single modulator. The optical single modulator has very good figures of merits : the measured on-off switching voltage of about 2.7V.

• Proceedings of the Korean Vacuum Society Conference
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• 2014.02a
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• pp.352.2-352.2
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• 2014

In this present work, we report a Cu-Mn alloy as a materials for the self-forming barrier process. And we investigated diffusion barrier properties of self-formed layer on low-k dielectrics with or without UV curing treatment. Cu alloy films were directly deposited onto low-k dielectrics by co-sputtering, followed by annealing at various temperatures. X-ray diffraction revealed Cu (111), Cu (200) and Cu (220) peaks for both of Cu alloys. The self-formed layers were investigated by transmission electron microscopy. In order to compare barrier properties between Mn-based interlayer interlayer, thermal stability was measured with various low-k dielectrics. X-ray photoelectron spectroscopy analysis showed that chemical compositions of self-formed layer. The compositions of the Mn based self-formed barriers after annealing were determined by the C concentration in the dielectric layers.

• Bulletin of the Korean Chemical Society
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• v.31 no.2
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• pp.291-297
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• 2010

This article introduces a facile nanoparticle self-assembly/annealing method for the preparation of nanoisland films. First, nanoparticle-polymer multilayer films are prepared with layer-by-layer assembly. Nanoparticle multilayer films are then annealed at $~500^{\circ}C$ in air to evaporate organic matters from the films. During the annealing process, the nanoparticles on the solid surface undergo nucleation and coalescence, resulting in the formation of nanostructured gold island arrays. By controlling the overall thickness (number of layers) of nanoparticle multilayer films, nanoisland films with various island density and different average sizes are obtained. The surface property of gold nanoisland films is further controlled by the self-assembly of alkanethiols, which results in an increased surface hydrophobicity of the films. The structure and characteristics of these nanoisland film arrays are found to be quite comparable to those of nanoisland films prepared by vacuum evaporation method. However, this self-assembly/annealing protocol is simple and requires only common laboratory supplies and equipment for the entire preparation process.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.35 no.1
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• pp.50-57
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• 2022

Reliability of CMOS has been severed under aggressive device scaling. Conventional technologies such as lightly doped drain (LDD) and forming gas annealing (FGA) have been applied for better device reliability, but further advances are modest. Alternatively, electro-thermal annealing (ETA) which utilizes Joule heat produced by electrodes in a MOSFET, has been newly introduced for gate dielectric curing. However, concerns about mechanical stability during the electro-thermal annealing, have not been discussed, yet. In this context, this paper demonstrates the mechanical stability of nanosheet FET during the electro-thermal annealing. The effect of mechanical stresses during the electro-thermal annealing was investigated with respect to device design parameters.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.19 no.5
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• pp.237-241
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• 2009

Dislocation dipoles were formed in the early stage of deformation of Y-CSZ single crystal at high temperatures. And the dipoles were pinched off to break into dipoles loops by dislocation climb. Dislocation loop annealing was peformed in Y-CSZ single crystal to evaluate the diffusivity of cation which was the rate-controlling ion.

• Proceedings of the Korean Vacuum Society Conference
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• 2013.08a
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• pp.214.2-214.2
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• 2013

Device performance for the 45 and 32 nm node CMOS technology requires the integration of ultralow-k materials. To lower the dielectric constant for PECVD and spin-on materials, partial replacement of the solid network with air (k=1.01) appears to be more intuitive and direct option. This can be achieved introducting of second "labile" phase during depositoin that is removed during a subsequent UV curing and annealing step. Besides, with shrinking line dimensions the resistivity of barrier films cannot meet the International Technology Roadmap for Semiconductors (ITRS) requirements. To solve this issue self-forming diffusion barriers have drawn attention for great potential technique in meeting all ITRS requirments. In this present work, we report a Cu-V alloy as a materials for the self-forming barrier process. And we investigated diffusion barrier properties of self-formed layer on low-k dielectrics with or without UV curing treatment. Cu alloy films were directly deposited onto low-k dielectrics by co-sputtering, followed by annealing at various temperatures. X-ray diffraction revealed Cu (111), Cu (200) and Cu (220) peaks for both of Cu alloys. The self-formed layers were investigated by transmission electron microscopy. In order to compare barrier properties between V-based interlayer on low-k dielectric with UV curing and interlayer on low-k dielectric without UV curing, thermal stability was measured with various heat treatment temperature. X-ray photoelectron spectroscopy analysis showed that chemical compositions of self-formed layer. The compositions of the V based self-formed barriers after annealing were strongly dominated by the O concentration in the dielectric layers.