• 전기전자학회논문지
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• 제22권3호
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• pp.548-557
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• 2018

In this paper, Asynchronous Self-Power Gating technique (ASPG) is used to reduce consumption power in asynchronous digital watch application. The power gating control signal is automatically generated by internal system operation characteristics instead of using replica circuit delay or four-phase handshaking protocol. Isolation cell is designed to insert it between power gating domain and normal operation domain. By using self-power gating circuit, asynchronous digital watch application consumes very low power and maintains data during sleep mode. The comparison results show the proposed ASPG technique saves leakage power up to 40.47% and delay time is reduced to 71% compared to the conventional circuit.

• Journal of Electrical Engineering and Technology
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• 제13권6호
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• pp.2479-2484
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• 2018

The filter bank multicarrier modulation (FBMC) technique is one of multicarrier modulation technique (MCM), which is mainly used to improve channel capacity of cognitive radio (CR) network and frequency spectrum access technique. The existing FBMC System contains serial to parallel converter, normal QAM modulation, Radix2 inverse FFT, parallel to serial converter and poly phase filter. It needs high area, delay and power consumption. To further reduce the area, delay and power of FBMC structure, a new clock gating technique is applied in the QAM modulation, radix2 multipath delay commutator (R2MDC) based inverse FFT and unified addition and subtraction (UAS) based FIR filter with parallel asynchronous self time adder (PASTA). The clock gating technique is mainly used to reduce the unwanted clock switching activity. The clock gating is nothing but clock signal of flip-flops is controlled by gate (i.e.) AND gate. Hence speed is high and power consumption is low. The comparison between existing QAM and proposed QAM with clock gating technique is carried out to analyze the results. Conversely, the proposed inverse R2MDC FFT with clock gating technique is compared with the existing radix2 inverse FFT. Also the comparison between existing poly phase filter and proposed UAS based FIR filter with PASTA adder is carried out to analyze the performance, area and power consumption individually. The proposed FBMC with clock gating technique offers low power and high speed than the existing FBMC structures.

• 한국산업정보학회논문지
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• 제19권4호
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• pp.33-39
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• 2014

본 논문에서는 나노미티 기술에서 HCI와 BTI와 같은 노화 현상에 의해 야기되는 MOSFET 디지털 회로의 실패를 정확히 예측을 위한 플립플롭 기반의 온-칩 노화 센싱 회로를 제안한다. 제안된 센싱 회로는 순차회로의 가드밴드 (guardband) 위반에 대한 경고를 나타내는 타이밍 윈도우를 이용해서 노화에 의한 회로의 동작 실패 전에 경고 비트를 발생한다. 발생된 비트는 고신뢰의 시스템 설계를 위한 적응형 셀프-튜닝 방법에서 제어 신호로 사용될 것이다. 노화 센싱 회로는 0.11um CMOS 기술을 사용해서 구현되었고, 파워-게이팅 구조를 가지는 $4{\times}4$ 곱셈기에 의해서 평가되었다.