Browse > Article
http://dx.doi.org/10.9723/jksiis.2014.19.4.033

Design and Implementation of a new aging sensing circuit based on Flip-Flops  

Lee, Jin-Kyung (대구대학교 전자공학과)
Kim, Kyung Ki (대구대학교 전자전기공학부)
Publication Information
Journal of Korea Society of Industrial Information Systems / v.19, no.4, 2014 , pp. 33-39 More about this Journal
Abstract
In this paper, a new on-chip aging sensing circuit based on flip-flops is proposed to detect a circuit failure of MOSFET digital circuits casued by aging phenomenon such as HCI and BTI. The proposed circuit uses timing windows to warn against a guardband violation of sequential circuits, and generates three warning bits right before circuit failures occur. The generated bits can apply to an adaptive self-tuning method for reliable system design as control signals. The aging sensor circuit has been implemented using 0.11um CMOS technology and evaluated by $4{\times}4$ multiplier with power gating structure.
Keywords
Aging phenomenon; HCI; BTI; NBTI; PBTI; Aging sensor circuit;
Citations & Related Records
Times Cited By KSCI : 3  (Citation Analysis)
연도 인용수 순위
1 Kyung Ki Kim, "Design of a New Adaptive Circuit to Compensate for Aging Effects of Nanometer Digital Circuits," Journal of the Korea Industrial Information System Society , V.18, No.6, pp. 25-30, 2013.   과학기술학회마을   DOI
2 Yeon-Bo Kim, Kyung Ki Kim, "The Impact of TDDB Failure on Nanoscale CMOS Digital Circuits," Journal of the Korea Industrial Information System Society, V.17, No.3, pp. 27-34, 2012.   과학기술학회마을   DOI
3 Kyung Ki Kim, "Analysis of Electromigr ation in Nanoscale CMOS Circuits," Journal of the Korea Industrial Information System Society, V.18, No.1, pp. 19-24, 2013.
4 M. Omana, D. Rossi, N. Bosio, And C. Metra, "Self-Checking Monitor For NBTI Due Degradation", In IEEE 16th International Mixed-Signals, Sensors and Systems Test Workshop, June 2010.
5 B. Paul, K. Kang, H. Kufluoglu, M. Ashraful Alam, & K. Roy, "Temporal Performance Degradation Under NBTI: Estimation And Design For Improved Reliability Of Nanoscale Circuits", Vol. 1, pp. 1-6, March 2006.
6 S. Mitra & M. Agarwal, "Circuit Failure Prediction To Overcome Scaled CMOS Reliability Challenges", IEEE International Test Conference, October 2007.
7 Intel, "3-D, 22nm: New Technology Delivers An Unprecedented Combination of Performance and Power Efficiency", http://www.intel.com/content/www/us/en/silicon-i nnovations/intel-22nm-technology.html, 2012.
8 S. N. Wooters, A. C. Cabe, Z. Qi, J. Wang, R. W. Mann, B. H. Calhoun, M. R. Stan, & T. N. Blalock, "Tracking On-Chip Age Using Distributed, Embedded Sensors", In IEEE Transactions On Very Large Scale Integration (VLSI) Systems, Vol. No. 99, pp. 1-12, 2011.
9 Z. Qi, J. Wang, A. Cabe, S. Wooters, T. Blalock, B. Calhoun, & M. Stan, "Sram-Based NBTI/PBTI Sensor System Design", In 47th ACM/IEEE Design Automation Conference, June 2010.
10 Agarwal M, Paul B, Zhang M, Mitra, S. Circuit failure prediction and its application to transistor aging. In: 25th IEEE VLSI test symposium; 2007. p. 277-86.
11 J. Vazquez, V. Champac, A. Ziesemer, R. Reis, I. Teixeira, M. Santos, And J. Teixeira, "Low- Sensitivity To Process Variations Aging Sensor For Automotive Safety-Critical Applications", In 28th VLSI Test Symposium (VTS), April 2010.