• Journal of Internet Computing and Services
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• v.4 no.3
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• pp.31-37
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• 2003

In this paper, an efficient non-scan design-for-testability (DFT) method for finite state machine(FSM) is proposed. The proposed method always guarantees short test pattern generation time and complete fault efficiency. It has a lower area overhead than full-scan and other non-scan DFT methods and enables to apply test patterns at-speed. The efficiency of the proposed method is demonstrated using well-known MCNC'91 FSM benchmark circuits.

• Transactions of the Korean Society of Mechanical Engineers
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• v.17 no.11
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• pp.2730-2741
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• 1993

A mathematical model of the seeker scan-loop which is composed of a spin-stabilized gyroscope and its driving signal processors is derived. The derived model has a transmission zero pair on the imaginary axis near to the required bandwidth. The LQG/LTR design methodology is evolved for the derived scan-loop model. To implement the designed LQG/LTR compensator to the actual plant, the compensator order is reduced using the internally balanced realization method. The performances of the LQG/LTR compensator are tested and compared with those of the P-control. Especially, stability-robustnessexperiments for model uncertainties represented in the form of time-delays are performed. It is demonstrated that the LQG/STR compensator is actually very robust to model uncertainties.

• Proceedings of the Korean Nuclear Society Conference
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• 2001.05a
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• pp.89.1-89
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• 2001

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.3
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• pp.85-97
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• 2002

STUMPS has been widely used for built-in self-test of scan design with multiple scan chains. In the STUMPS architecture, there is very high correlation between the bit sequences in the adjacent scan chains. This correlation causes circuits lower the fault coverage. In order to solve this problem, an extra combinational circuit block(phase shifter) is placed between the LFSR and the inputs of STUMPS architecture despite the hardware overhead increase. This paper introduces an efficient test pattern generation technique and built-in self-test architecture for sequential circuits with multiple scan chains. The proposed test pattern generator is not used the input of LFSR and phase shifter, hence hardware overhead can be reduced and sufficiently high fault coverage is obtained. Only several XOR gates in each scan chain are required to modify the circuit for the scan BIST, so that the design is very simple.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.6
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• pp.70-76
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• 2015

This paper introduces an FPGA self-test architecture reusing FPGA boundary scan chain as self-test circuits. An FPGA boundary scan cell is two or three times bigger than a normal boundary scan cell because it is used for configuring the function of input/output pins functions as well as testing and debugging. Accordingly, we analyze the architecture of an FPGA boundary scan cell in detail and design a set of built-in self-test (BIST) circuits in which FPGA boundary scan chain and a small amount of FPGA logic elements. By reusing FPGA boundary scan chain for self-test, we can reduce area overhead and perform a processor based on-board FPGA testing/monitoring. Experimental results show the area overhead comparison and simulation results.

• Journal of Institute of Control, Robotics and Systems
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• v.10 no.2
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• pp.178-184
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• 2004

In this paper, we designed an image processing system for the high speed line-scan camera which adopts the new memory model we proposed. As a resolution and a data rate of the line-scan camera are becoming higher, the faster image processing systems are needed. But many conventional systems are not sufficient to process the image data from the line-scan camera during a very short time. We designed the memory controller which eliminates the time for transferring image data from the line-scan camera to the main memory with high-speed SRAM and has a dual-port configuration therefore the DSP can access the main memory even though the memory controller are writing the image data. The memory controller is implemented by VHDL and Xilinx SPARTAN-IIE FPGA.

• Journal of the Korean Institute of Telematics and Electronics S
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• v.35S no.5
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• pp.35-41
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• 1998

This paper presents a decoupling controller of the missile seeker scan loop with a spin-stabilized platform. A precise seeker motion with respect to the scan command is essential for the higher acquisition probability of the target. As the seeker scan loop is a deeply cross-coupled two input two output system, an accurate pointing or scanning for each axis to the target is very difficult, even though provided with the help of a high performance controller. When a decoupling control is applied to the seeker scan loop, the cross-coupling between two axes can be reduced to a remarkable amount. As a low order of controller is required for the real time operation, a PI controller with decoupling filter is suggested and compared with other controllers. A linearized dynamic model of seeker scan loop is used and validated through the comparison of experimental results of step responses.

• Fashion & Textile Research Journal
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• v.22 no.5
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• pp.595-606
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• 2020

This study develops an optimal two-dimensional (2D) pattern from three-dimensional human scan data by considering the cycling posture and dermatome of high school male cyclists. By analyzing the body surface change in the cycling posture and considering the dermatome of the lower limbs, the optimal cutting line setting and the development of cycling tights for individual cyclists were presented to provide data that could be used in the clothing industry. We designed three cycling tights to solve the size unsuitability. 3D design 1 is a non-extension design based on the analysis of the 3D human body scan data, in which parts were connected diagonally from the front of the knee to the back of the knee. 3D design 2 removed both the front and back to reduce air resistance during cycling. 3D design 3 did not have a cutting line on the front panel because of the air resistance during cycling in the front area. We analyzed the garment pressure for 8 points of lower body and performed a subjective evaluation of the 3D designed tights and the current cycling tights. The 3D design 1 in this study was well received in the omphalion, thigh, and hip area, while 3D design 3 was well received in the omphalion, thigh, hip, and bottom bands. Therefore, the LoNE of 3D design 1 was applied to the front, and the hip cutting line of 3D design 3 was applied to the back.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2000.11a
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• pp.866-869
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• 2000

To improve quality of the ground surface, we have to consider a number of parameters. But it is difficult to make experiment with many parameters. Most of all experiments try to search optimal grinding condition with conservative factors such as feed rate, depth of cut, wheel rotating speed, etc. But This paper attempts to view the significance of some different factors effecting on the surface roughness by introducing helical scan grinding method and material removal rate. The design of experiment is used to find the optimal grinding condition which minimizes the surface roughness value bout optical glass material. To analyze experimental results, ANOVA(ANalysis of VAriation) is used. Discussion on the result about helical scan grinding is also given.

• Journal of Veterinary Clinics
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• v.35 no.3
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• pp.93-96
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• 2018

This study aimed to establish an injection protocol to determine the precise CT scan timing in canine abdominal multi-phase CT using the test bolus method. Three dynamic scans with different contrast injection parameters were performed using a crossover design in eight normal beagle dogs. A contrast material was administered at a fixed dose of 200 mg iodine/kg as a test bolus for dynamic scans 1 and 2, and 600 mg iodine/kg as a main bolus for dynamic scan 3. The contrast materials were administered with 1 ml/s in dynamic scan 1, and 3 ml/s in dynamic scan 2 and 3. The mean arrival time to the appearance of aortic enhancement in dynamic scan 3 was similar to that in dynamic scan 2, and different significantly to that in dynamic scan 1. The mean arrival time to the peak aortic and pancreatic parenchymal enhancement in dynamic scan 3 was similar to that in dynamic scan 1, and different significantly to that in dynamic scan 2. In multi-phase CT scan, a test bolus should be injected with the same injection duration of a main bolus, to obtain the precise arrival times to peak of arterial or pancreatic parenchymal enhancement.