• Proceedings of the Materials Research Society of Korea Conference
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• 2003.11a
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• pp.63-63
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• 2003

The nanotopography of silicon wafers has emerged as an important factor in the STI process since it affects the post-CMP thickness deviation (OTD) of dielectric films. Ceria slurry with surfactant is widely applied to STI-CMP as it offers high oxide-to-nitride removal selectivity. Aiming to control the nanotopography impact through ceria slurry characteristics, we examhed the effect of surfactant concentration and abrasive size on the nanotopography impact. The ceria slurries for this study were produced with cerium carbonate as the starting material. Four kinds of slurry with different size of abrasives were prepared through a mechanical treatment The averaged abrasive size for each slurry varied from 70 nm to 290 nm. An anionic organic surfactant was added with the concentration from 0 to 0.8 wt %. We prepared commercial 8 inch silicon wafers. Oxide Shu were deposited using the plasma-enhanced tetra-ethyl-ortho-silicate (PETEOS) method, The films on wafers were polished on a Strasbaugh 6EC. Film thickness before and after CMP was measured with a spectroscopic ellipsometer, ES4G (SOPRA). The nanotopogrphy height of the wafer was measured with an optical interferometer, NanoMapper (ADE Phase Shift)

• Proceedings of the Korean Society of Tribologists and Lubrication Engineers Conference
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• 2002.10b
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• pp.439-440
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• 2002

Nano-Crystalline $CeO_2$ particles were dispersed in deionized water with controlled slurry chemicals for CMP test. According to the CMP test, the removal rate of $SiO_2$ layer was mainly controlled by the size and crystallinity of $CeO_2$ particles which can be controlled by the heat-treatment condition during $CeO_2$ synthesis. In contrast, the removal rate of $Si_3N_4$ layer was significantly influenced by the passivation reagent which protects the $Si_3N_4$ surface layer from excessive dissolution during CMP.

• Proceedings of the IEEK Conference
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• 1998.06a
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• pp.481-484
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• 1998

In this study, oxide(TEOS) CMPs were carried out for various head pressures. Table and head speeds are fixed at 25 RPM. Head pressures are 5, 7.5, 10, 12.5 PSI, and under these conditions, 1,587, 1,631, 2,556, 2,871.agns./min of oxide (TEOS) removal rates and 14.7, 18.5, 9.52, 7.9% of uniformities are obtained, respectively. Also, these experiments for local and global planarizations were done using the patterned 4" wafers. These conditions are applicable to STI(shallow trench isolation) structures and planarizations for sub-half micron lithography.aphy.

• Journal of the Korean Ceramic Society
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• v.40 no.2
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• pp.167-171
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• 2003

CMP(Chemical Mechanical Planarization) slurry for STI process is made by mechanically synthesized$CeO_2$as abrasive. The abrasive can be stabilized by electrostatic or steric stabilization in aqueous slurry and steric stabilization is more effective for long-term stability. Blanket-type$SiO_2$and $Si_3N_4$ wafers are polished with CMP slurry containing$CeO_2$synthesized in 50$0^{\circ}C$ or $700^{\circ}C$. Removal rate and surface uniformity of$SiO_2$and$Si_3N_4$wafer and selectivity are influenced by synthetic condition of abrasive, suspension stability and pH of slurries.

• Proceedings of the Materials Research Society of Korea Conference
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• 2011.10a
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• pp.23-23
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• 2011

Chemical-Mechanical Planarization (CMP) 공정이란 화학적 반응 및 기계적인 힘이 복합적으로 작용하여 표면을 평탄화하는 공정이다. 이러한 CMP 공정은 반도체 산업에서 회로의 고집적화와 다층구조를 형성하기 위하여 도입되었으며 반도체 제조를 위한 필수공정으로 그 중요성이 강조되고 있다. 특히 최근에는 Inter-Level Dielectric (ILD)의 형성과 Shallow Trench Isolation (STI) 공정에서실리콘 산화막을 평탄화하기 위한 CMP 공정에 대해 연구가 활발히 이루어지고 있다. 그러나 CMP 공정 후 scratch, pitting corrosion, contamination 등의 Defect가 발생하는 문제점이 존재한다. 이 중에서도 scratch는 기계적, 열적 스트레스에 의해 생성된 패드의 잔해, 슬러리의 잔유물, 응집된 입자 등에 의해 표면에 형성된다. 반도체 공정에서는 다양한 종류의 실리콘 산화막이 사용되고 gks이러한 실리콘 산화막들은 종류에 따라 경도가 다르다. 따라서 실리콘 산화막의 경도에 따른 CMP 공정 및 이로 인한 Scratch 발생에 관한 연구가 필요하다고 할 수 있다. 본 연구에서는 scratch 형성의 거동을 알아보기 위하여 boronphoshposilicate glass (BPSG), plasma enhanced chemical vapor deposition (PECVD) tetraethylorthosilicate (TEOS), high density plasma (HDP) oxide의 3가지 실리콘 산화막의 기계적 성질 및 이에 따른 CMP 공정에 대한 평가를 실시하였다. CMP 공정 후 효율적인 scratch 평가를 위해 브러시를 이용하여 1차 세정을 실시하였으며 습식세정방법(SC-1, DHF)으로 마무리 하였다. Scratch 개수는 Particle counter (Surfscan6200, KLA Tencor, USA)로 측정하였고, 광학현미경을 이용하여 형태를 관찰하였다. Scratch 평가를 위한 CMP 공정은 실험에 사용된 3가지 종류의 실리콘 산화막들의 경도가 서로 다르기 때문에 동등한 실험조건 설정을 위해 동일한 연마량이 관찰되는 조건에서 실시하였다. 실험결과 scratch 종류는 그 형태에 따라 chatter/line/rolling type의 3가지로 분류되었다 BPSG가 다른 종류의 실리콘 산화막에 비해 많은 수에 scratch가 관찰되었으며 line type이 많은 비율을 차지한다는 것을 확인하였다. 또한 CMP 공정에서 압력이 증가함에 따라 chatter type scratch의 길이는 짧아지고 폭이 넓어지는 것을 확인하였다. 본 연구를 통해 실리콘 산화막의 경도에 따른 scratch 형성 원리를 파악하였다.

• Proceedings of the Korean Ceranic Society Conference
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• 2003.04a
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• pp.78.2-78
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• 2003

• Proceedings of the Materials Research Society of Korea Conference
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• 1998.08a
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• pp.78.2-78
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• 1998

• Proceedings of the Materials Research Society of Korea Conference
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• 1998.08a
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• pp.106.1-106
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• 1998

• Transactions on Electrical and Electronic Materials
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• v.8 no.1
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• pp.1-4
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• 2007

This paper discusses two approaches for pre-polishing optimization of oxide chemical mechanical planarization (CMP) that can be used as alternatives to the commonly applied dummy structure insertion in shallow trench isolation (STI) and replacement gate (RG) technologies: reverse nitride masking (RNM) and oxide etchback (OEB). Wafers have been produced using each optimization technique and CMP tests have been performed. Dishing, erosion and global planarity have been investigated with the help of conductive atomic force microscopy (C-AFM). The results demonstrate the effectiveness of both techniques which yield excellent planarity without dummy structure related performance degradation due to capacitive coupling.

• Proceedings of the Materials Research Society of Korea Conference
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• 2006.11a
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• pp.15.1-15.1
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• 2006