• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.14 no.1
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• pp.1-5
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• 2001

STI(shallow trench isolation)-CMP(chemical mechanical polishing) process have been substituted for LOCOS(local oxidation of silicon) process to obtain global planarization in the below sub-0.5㎛ technology. However TI-CMP process, especially TI-CMP with RIE(reactive ion etching) etch back process, has some kinds of defect like nitride residue, torn oxide defect, etc. In this paper, we studied how to reduced torn oxide defects after STI-CMP with RIE etch back processed. Although torn oxide defects which can occur on trench area is not deep and not severe, torn oxide defects on moat area is not deep and not severe, torn oxide defects on moat area is sometimes very deep and makes the yield loss. Thus, we did test on pattern wafers which go through trench process, APECVD process, and RIE etch back process by using an IPEC 472 polisher, IC1000/SUVA4 PAD and KOH base slurry to reduce the number of torn defects and to study what is the origin of torn oxide defects.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.21 no.3
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• pp.203-207
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• 2008

Chemical mechanical polishing (CMP) allows the planarization of wafers with two or more materials. There are many elements such as slurry, polishing pad, process parameters and conditioning in CMP process. Especially, polishing pad is considered as one of the most important consumables because this affects its performances such as WIWNU(within wafer non-uniformity) and MRR(material removal rate). In polishing pad, grooves and pores on its surface affect distribution of slurry, flow and profile of MRR on wafer. A subject of this investigation is to apply CMP for planarization of shallow trench isolation structure using microstructure(MS) pad. MS pad is designed to have uniform structure on its surface and manufactured by micro-molding technology. And then STI CMP performances such as pattern selectivity, erosion and comer rounding are evaluated.

• Transactions on Electrical and Electronic Materials
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• v.3 no.3
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• pp.18-20
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• 2002

In sub-l/4 ${\mu}{\textrm}{m}$ NMOSFET with STI (Shallow Trench Isolation), the anomalous hump phenomenon of subthreshold region, due to capped p-TEOS/SiN induced defect, is reported. The hump effect was significantly observed as channel length is reduced, which is completely different from previous reports. Channel boron dopant redistribution due to the defect should be considered to improve hump characteristics besides considerations of STI comer and recess. 130

• JSTS:Journal of Semiconductor Technology and Science
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• v.3 no.2
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• pp.69-75
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• 2003

Cell transistor and data retention time characteristics were studied in 90 nm design rule 512M-bit DRAM, for the first time. And, the characteristics of cell transistor are investigated for different STI gap-fill materials. HDP oxide with high compressive stress increases the threshold voltage of cell transistor, whereas the P-SOG oxide with small stress decreases the threshold voltage of cell transistor. Stress between silicon and gap-fill oxide material is found to be the major cause of the shift of the cell transistor threshold voltage. If high stress material is used for STI gap fill, channel-doping concentration can be reduced, so that cell junction leakage current is decreased and data retention time is increased.

• Proceedings of the Korean Society of Tribologists and Lubrication Engineers Conference
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• 2003.11a
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• pp.402-402
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• 2003

• Transactions on Electrical and Electronic Materials
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• v.5 no.5
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• pp.169-172
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• 2004

Deep sub-micron device required to get the superior ultra thin gate oxide characteristics. In this research, I will recommend a novel shallow trench isolation structure(STI) for thin gate oxide and a $N_2$O gate oxide 30 $\AA$ by NO ambient process. The local oxidation of silicon(LOCOS) isolation has been replaced by the shallow trench isolation which has less encroachment into the active device area. Also for $N_2$O gate oxide 30 $\AA$, ultra thin gate oxide 30 $\AA$ was formed by using the $N_2$O gate oxide formation method on STI structure and LOCOS structure. For the metal electrode and junction, TiSi$_2$ process was performed by RTP annealing at 850 $^{\circ}C$ for 29 sec. In the viewpoints of the physical characteristics of MOS capacitor, STI structure was confirmed by SEM. STI structure was expected to minimize the oxide loss at the channel edge. Also, STI structure is considered to decrease the threshold voltage, result in a lower Ti/TiN resistance( Ω /cont.) and higher capacitance-gate voltage(C- V) that made the STI structure more effective. In terms of the TDDB(sec) characteristics, the STI structure showed the stable value of 25 % ～ 90 % more than 55 sec. In brief, analysis of the ultra thin gate oxide 30 $\AA$ proved that STI isolation structure and salicidation process presented in this study. I could achieve improved electrical characteristics and reliability for deep submicron devices with 30 $\AA$ $N_2$O gate oxide.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2005.11a
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• pp.356-357
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• 2005

Chemical mechanical polishing (CMP) allows the planarization of wafers with two or more materials at their surfaces. Especially, polishing pad is considered as one of the most important consumables because of its properties. Subject of this investigation is to apply CMP for planarization of shallow trench isolation structure using microstructure pad. Microstructure pad is designed to have uniform structure on its surface and fabricated by micro-molding technology. And then STI CMP performances such as oxide dishing and nitride corner rounding are evaluated.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.13 no.9
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• pp.729-734
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• 2000

Recently, Very Large Scale Integrated (VLSI) circuit & deep-submicron bulk Complementary Metal Oxide Semiconductor(CMOS) devices require gate electrode materials such as metal-silicide, Titanium-silicide for gate oxides. Many previous authors have researched the improvement sub-micron gate oxide quality. However, few have reported on the electrical quality and reliability on the ultra thin gate oxide. In this paper, at first, I recommand a novel shallow trench isolation structure to suppress the corner metal-oxide semiconductor field-effect transistor(MOSFET) inherent to shallow trench isolation for sub 0.1${\mu}{\textrm}{m}$ gate oxide. Different from using normal LOCOS technology deep-submicron CMOS devices using novel Shallow Trench Isolation(STI) technology have a unique"inverse narrow-channel effects"-when the channel width of the devices is scaled down, their threshold voltage is shrunk instead of increased as for the contribution of the channel edge current to the total channel current as the channel width is reduced. Secondly, Titanium silicide process clarified that fluorine contamination caused by the gate sidewall etching inhibits the silicidation reaction and accelerates agglomeration. To overcome these problems, a novel Two-step Deposited silicide(TDS) process has been developed. The key point of this process is the deposition and subsequent removal of titanium before silicidation. Based on the research, It is found that novel STI structure by the SEM, in addition to thermally stable silicide process was achieved. We also obtained the decrease threshold voltage value of the channel edge. resulting in the better improvement of the narrow channel effect. low sheet resistance and stress, and high threshold voltage. Besides, sheet resistance and stress value, rms(root mean square) by AFM were observed. On the electrical characteristics, low leakage current and trap density at the Si/SiO$_2$were confirmed by the high threshold voltage sub 0.1${\mu}{\textrm}{m}$ gate oxide.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.4
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• pp.427-435
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• 2014

Segmented-channel MOSFETs (SegFETs) can achieve both good performance and variation robustness through the use of $HfO_2$ (a high-k material) to create the shallow trench isolation (STI) region and the very shallow trench isolation (VSTI) region in them. SegFETs with both an HTI region and a VSTI region (i.e., the STI region is filled with $HfO_2$, and the VSTI region is filled with $SiO_2$) can meet the device specifications for high-performance (HP) applications, whereas SegFETs with both an STI region and a VHTI region (i.e., the VSTI region is filled with $HfO_2$, and the STI region is filled with $SiO_2$) are best suited to low-standby power applications. AC analysis shows that the total capacitance of the gate ($C_{gg}$) is strongly affected by the materials in the STI and VSTI regions because of the fringing electric-field effect. This implies that the highest $C_{gg}$ value can be obtained in an HTI/VHTI SegFET. Lastly, the three-dimensional TCAD simulation results with three different random variation sources [e.g., line-edge roughness (LER), random dopant fluctuation (RDF), and work-function variation (WFV)] show that there is no significant dependence on the materials used in the STI or VSTI regions, because of the predominance of the WFV.

• Transactions on Electrical and Electronic Materials
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• v.2 no.3
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• pp.24-27
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• 2001

The end point of oxide chemical mechanical polishing (CMP) have determined by polishing time calculated from removal rate and target thickness of oxide. This study is about control of oxide removal amounts on the shallow trench isolation (STI) patterned wafers using removal rate and thickness of blanket (non-patterned) wafers. At first, it was investigated the removal properties of PETEOS blanket wafers, and then it was compared with the removal properties and the planarization (step height) as a function of polishing time of the specific STI patterned wafers. We found that there is a relationship between the oxide removal amounts of blanket and patterned wafers. We analyzed this relationship, and the post CMP thickness of patterned wafers could be controlled by removal rate and removal target thickness of blanket wafers. As the result of correlation analysis, we confirmed that there was the strong correlation between patterned and blanket wafer (correlation factor: 0.7109). So, we could confirm the repeatability as applying for STI CMP process from the obtained linear formula. As the result of repeatability test, the differences of calculated polishing time and actual polishing time was about 3.48 seconds. If this time is converted into the thickness, then it is from 104 $\AA$ to 167 $\AA$. It is possible to be ignored because process margin is about 1800 $\AA$.