• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.2
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• pp.273-278
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• 2012

In this contribution, we design and implement an SPI hardware interface for the microprocessor to communicate with the MMC (Multi-Media Card) in an embedded system. Proposed architecture is compatible with the APB in AMBA bus architecture. Embedding OS in an embedded system means a big burden in terms of hardware and software ending up with performance decline. In this paper, we adopt the concept of SPI communication without using OS in the embedded system and implement in a form of FPGA chip. The designed SPI module was automatically synthesized, placed, and routed. Implementation was performed through the Altera FPGA and well operated at 25MHz clock frequency, which satisfied our target speed.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.8 no.3
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• pp.577-585
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• 2004

System Packet Interface Level 4 Phase(SPI-4.2) is an interface for packet and cell transfer between a physical layer(PHY) device and a link layer device, for aggregate bandwidths of OC-192 ATM and Packet Over Sonet/SDH(POS), as well as 10Gbps Ethernet applications. In this paper, we performs the research for SPI-4.2. Also we analyze the performance of SPI-4.2 interface module after modeling using C programming language. This paper shows that SPI-4.2 interface module with 512-word FIFO depth is able to be adapted for the offered loads to 97％ in random uniform traffic and 94％ in bursty traffic with bursty length 32. SPI-4.2 interface module can experience an performance degradation due to heavy overhead when it massively receives small size packets less than 14-byte. SPI-4.2 interface module is suited for line cards in gigabit/terabit routers, and optical cross-connect switches, and SONET/SDH-based transmission systems.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.8 no.6
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• pp.1107-1114
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• 2004

System Packet Interface Level 4 Phase 2(SPI-4.2) is an interface for packet and cell transfer between a physical layer(PHY) device and a link layer device, for aggregate bandwidths of OC-192 ATM and Packet Over Sonet/SDH(POS), as well as 10Gbps Ethernet applications. SPI-4.2 core consists of Tx and Rx modules and supports full duplex communication. Tx module of SPI-4.2 core writes 64-bit data word and 14-bit header information from the user interface into asynchronous FIFO and transmits DDR(Double Data Rate) data over PL4 interface. Rx module of SPI-4.2 core operates in vice versa. Tx and Rx modules of SPI-4.2 core are designed to support maximum 256-channel and control the bandwidth allocation by configuring the calendar memory. Automatic DIP4 and DIP-2 parity generation and checking are implemented within the designed core. The designed core uses Xilinx ISE 5.li tool and is described in VHDL Language and is simulated by Model_SIM 5.6a. The designed core operates at 720Mbps data rate per line, which provides an aggregate bandwidth of 11.52Gbps. SPI-4.2 interface core is suited for line cards in gigabit/terabit routers, and optical cross-connect switches, and SONET/SDH-based transmission systems.

• Journal of the Korea Convergence Society
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• v.13 no.4
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• pp.53-61
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• 2022

Accidents are steadily occurring due to machine defects and carelessness during LNG storage operations. In previous studies, an environmental sensor module capable of measuring pressure, temperature, gas concentration, and flow to detect danger in advance was developed and the response speed according to the amount of leaked gas was measured. This paper proposes the development of a wired and wireless communication module that transmits data measured by the environmental sensor module to embedded devices connected to wired and wireless networks of SPI, UART, and LTE. First, a data communication module capable of interworking with an environmental sensor is designed. Design a protocol between devices in the Local Control Part and wired and wireless protocols in the Local Control Part and Remote Control Part. Ethernet, WiFi, and LTE communication modules were designed, and UART and SPI channels that can be linked with embedded controllers were designed. As a result, it was confirmed through a UI (User Interface) that each embedded device transmits data measured by the environmental sensor module while simultaneously communicating on a wired and wireless basis.

• The Journal of the Convergence on Culture Technology
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• v.1 no.3
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• pp.83-85
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• 2015

It has been increased that communicate each other things such as consumer electronics, mobile equipments and wearable computer with serial communication protocol. The conventional method of SPI and I2C high speed serial communication is widely used with 2 pin of clock and data pin. It has been more important than the speed of data transfer to simplify the hardware structure because the IoT components is reduced the hardware complexity. In this paper, we describe the protocol and implementation of serial data transfer with only one pin. The proposed protocol is suitable for the mobile products that send and receive the small amount of data with low speed and low power consumption.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.24 no.10
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• pp.1361-1368
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• 2020

The system for counting the number of people has traditionally been implemented in various ways. Existing systems include infrared sensors, lasers, cameras, etc. In the case of such an existing system, there are restrictions on space such as ceilings and sides of walls. In this paper, we propose a method of detecting the footsteps of pedestrians using a piezoelectric mat containing a number of piezoelectric sensors and counting the number of pedestrians passing simultaneously by using the data collected from the piezoelectric mat. When pedestrians pass over piezoelectric mats, the collected sensor data was aggregated using SPI communication and transmitted to PC server using TCP/IP communication. Performance analysis shows that approximately 600 step data can be recognized with 99% accuracy. This is to overcome the shortcomings of other counting systems.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.15 no.6
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• pp.251-255
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• 2015

In this paper, we propose a fuse controller which is used for storing the optimal value or the correction value for the surrounding product of the IoT applications and it is implemented serial communication circuit using a single pin. Because of the proposed single pin protocol is simpler in the hardware than the conventional $I^2C$ and SPI using two or more pins, it is suitable for the area of small amount of data transmission. The function of the one pin protocol is verified by logic simulation and the FPGA test board and it is fabricated using CMOS 0.35um technology. It is expected to use the IoT product that require the low power consumption and simple hardware.

• Journal of IKEEE
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• v.26 no.3
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• pp.437-444
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• 2022

This paper proposes a CRC error verification method for SPI and I2C buses of automotive semiconductors. In automotive semiconductors, when an error occurs in communication and an incorrect value is transmitted, fatal results may occur. Unlike LIN communication and CAN communication, in communication such as SPI and I2C, there is no frame for detecting an error, so some definitions of new standards are required. Therefore, in this paper, the CRC error detection mode is newly defined in the SPI and I2C communication protocols, and the verification is presented by designing it in hardware.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2011.10a
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• pp.185-187
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• 2011

최근 선박 및 물류 자동화는 물류 증대와 함께 선박의 운용을 더욱 복잡하게 만들고 있으며, 선박 내부의 통신 장비 및 통신 시스템의 구성 또한 매우 복잡하게 구성되어 있다. 때문에 지금 현재의 통신장비의 내부 통신 프로토콜은 일반적인 RS-422,485 기반의 NMEA-0183과 CAN 통신 기반의 NMEA-2000 기반으로 해상전자장비의 인터페이스 표준으로 법제화 되어있다. 본 논문에서는 가장 일반적인 NMEA-0183 프로토콜을 7-체널의 NMEA-0183 시리얼 통신 데이터를 지원하도록 설계하였으며, 그 외에 SPI 방식의 3-체널 16비트 ADC(Analog Digital Converter)와 SPI 방식의 2-체널 펄스(pulse) 입력을 받을 수 있도록 설계하였다. 특히, 선박용 통신장비의 중요한 7가지로 한정하여 설계하였다. 본 연구의 소형화를 통하여 이동이 가능하도록 하여 그 편리성을 제공하고, 소형 PC 기반의 중앙 모니터링 시스템을 구현하여 다체널 인디케이트 시스템의 효율성을 제시하고자 한다.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.5
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• pp.1095-1101
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• 2012

This paper presents a design of a BLDC servo motor control system for the auto process of assembly and supply using DSP(Digital Signal Processor) controller and IGBT driver. The assembly and supply auto processing system needs torque, speed, position control of servo motor for variable action. This paper implements those servo control with vector control and space vector PWM(Pulse Width Modulation) technique. As CPU of controller, TMS320F240 DSP was adopted because it has PWM waveform generator, A/D converter, SPI(Serial Peripheral Interface) port and many input/output port etc. This control system consists of 3-level hierarchy structure that main host PC manages three sub DSP system which transfer downward command and are monitoring the states of end servo controllers. Each sub DSP system operates eight BLDC servo controllers which control BLDC motor using DSP and IPM. Between host system and sub DSP communicate with RS-422, between main processor and controller communicate with SPI port.