• Journal of the Korean Institute of Telematics and Electronics D
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• v.36D no.8
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• pp.54-61
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• 1999

This paper proposes a new optic link structure applicable to broad-band wireless access microcellularsystem servicing in the millimeter wave frequency band. The proposed structure utilizes photonic mixing by exploiting the nonlinear property of EOMs, which leads to the frequency up-conversion at the CS and thus, electrical mixing at a BS is not required. Moreover, via transmitting an additional optical millimeter wave carrier into the Bs, the dispenses with an active optic source, which miniaturizes the BS. We analyze CNR, IM3/C in the downlink and SFDR in the uplink. Through simulation using the typical parameter values we also show the feasibility of the proposed system based on the requirements in the current microcellular system.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.1
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• pp.56-63
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• 2008

This paper describes a 12 bit 1GS/s current mode segmented DAC for WCDMA communication. The proposed circuit in this paper employes segmented structure which consists of 4bit binary weighted structure in the LSB and 4bit thermometer decoder structure in the mSB and MSB. The proposed DAC uses delay time compensation circuits in order to suppress performance decline by delay time in segmented structure. The delay time compensation circuit comprises of phase frequency detector, charge pump, and control circuits, so that suppress delay time by binary weighted structure and thermometer decoder structure. The proposed DAC uses CMOS $0.18{\mu}m$ 1-poly 6-metal n-well process, and measured INL/DNL are below ${\pm}0.93LSB/{\pm}0.62LSB$. SFDR is approximately 60dB and SNDR is 51dB at 1MHz input frequency. Single DAC's power consumption is 46.2mW.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.8
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• pp.580-587
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• 2003

In this paper, we introduce a novel model to analyze the linearity of a TW-EAM (traveling-wave electroabsorption modulator). The device length, microwave loss (ML), and internal reflection (IR) due to impedance mismatch have effect on the linearity of a TW-EAM. The longer devices have characteristics of lower biases with minimum IMDS (intermodulation distortions). ML decreases the output power as well as the IMD value. Internal reflection has different nonlinear characteristics according to the wavelength of the input frequency and the device length. There is little change in SFDR (spurious-free dynamic range) due to ML or IR. As a result, for a 50 GHz band RF-optical communication system, a 0.8 mm-long TW-EAM with the lowest ML would have better properties by using n, which is caused by impedance, mismatch at the output port.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.5C
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• pp.395-402
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• 2008

In this paper, an I/Q channel 12bits 40MS/s Pipeline Analog to Digital Converter that is able to apply to WLAN/WMAN system is proposed. The proposed ADC integrates DLL based duty-correction circuit which corrects the fluctuations in the duksty cycle caused by miniaturization of CMOS devices and faster operating speeds. It is designed as a 1% to 99% input clock duty cycle could be corrected to 50% output duty cycle. The prototype ADC is implemented in a $0.18{\mu}m$ CMOS n-well 1-poly 6-metal process and dissipates 184mW at 1.8V single supply The SNDR of the proposed 12bit ADC is 52dB and SFDR of 59dBc(@Fs=20MHz, Fin=1MHz) is measured.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.13 no.1
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• pp.8-16
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• 2020

In this paper, a single-bit 2nd-order delta-sigma modulator with the architecture of cascaded-of-integrator feedforward (CIFF) is proposed for column-parallel analog-to-digital converter (ADC) array used in a low noise CMOS image sensor. The proposed modulator implements two switched capacitor integrators and a single-bit comparator within only 10-㎛ column-pitch for column-parallel ADC array. Also, peripheral circuits for driving all column modulators include a non-overlapping clock generator and a bias circuit. The proposed delta-sigma modulator has been implemented in a 110-nm CMOS process. It achieves 88.1-dB signal-to-noise-and-distortion ratio (SNDR), 88.6-dB spurious-free dynamic range (SFDR), and 14.3-bit effective-number-of-bits (ENOB) with an oversampling ratio (OSR) of 418 for 12-kHz bandwidth. The area and power consumption of the delta-sigma modulator are 970×10 ㎛2 and 248 ㎼, respectively.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.15 no.5
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• pp.335-342
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• 2022

In this paper, a single-bit 3rd-order feedforward delta sigma modulator is proposed for audio applications. The proposed modulator is based on a class-C inverter for low voltage and power applications. For the high-precision requirement, the class-C inverter with regulated cascode structure increases its DC gain and acts as a low-voltage subthreshold amplifier. The proposed Class-C inverter-based modulator is designed and simulated in 180-nm CMOS process. With no performance loss and a low supply voltage compatibility, the proposed class-C inverter-based switched-capacitor modulator achieves high power efficiency. This design achieves an signal-to-noise-and-distortion ratio (SNDR) of 93.9 dB, an signal-to-noise ratio (SNR) of 108 dB, an spurious-free dynamic range (SFDR) of 102 dB, and a dynamic range (DR) of 102 dB at a signal bandwidth of 20 kHz and a sampling frequency of 4 MHz, while only using 280 μW of power consumption from a 0.8-V power supply.

• Proceedings of the IEEK Conference
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• 2004.06b
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• pp.545-548
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• 2004

The paper describes the design of high-speed, high-resolution Sample-and-Hold circuit which shows the conversion rate 80MHz and the power supply of 3.3v with 0.35um CMOS 2-poly 4-metal process for high-speed, high resolution Analog-to-Digital Converter. For improving Dynamic performance of Sample-and-Hold, Two Double bootstrap switch and high performance operational amplifier with gain booster, which are used. and For physical stability of Sample and Hold circuit, reduces excess voltage of gate in bootstrap switch. Simulation results using HSPICE shows the SFDR of 71dB, 75dB in conversion rate of 80MHz result for two inputs(0.5Vpp, 10MHz and 1Vpp, 10MHz) and the power dissipation of 48mW at single 3.3V supply voltage.

• JSTS:Journal of Semiconductor Technology and Science
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• v.12 no.3
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• pp.270-277
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• 2012

This paper presents a new DAC design strategy to achieve a wideband dynamic linearity by increasing the bandwidth of the output impedance. In order to reduce the dominant parasitic capacitance of the conventional matrix structure, all the cells associated with a unit current source and its control are stacked in a single column very closely (stacked unit cell structure). To further reduce the parasitic capacitance, the size of the unit current source is considerably reduced at the sacrifice of matching yield. The degraded matching of the current sources is compensated for by a self-calibration. A prototype 6-bit 3.3-GS/s current-steering full binary DAC was fabricated in a 1P9M 90 nm CMOS process. The DAC shows an SFDR of 36.4 dB at 3.3 GS/s Nyquist input signal. The active area of the DAC occupies only $0.0546mm^2$ (0.21 mm ${\times}$ 0.26 mm).

• 한국정보통신설비학회:학술대회논문집
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• 2007.08a
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• pp.19-21
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• 2007

디지털용 Uncooled DFB 레이저 다이오드를 이용하여 광대역 아날로그 피드포워드 광송신기를 제작하였다. 광송신기의 상호변조왜곡 성분 및 잡음성분을 제거하기 위해 광 피드포워드 보상기법을 사용하였으며, 다중서비스를 위해 $2.05{\sim}2.60$ GHz(550 MHz)에서 상호 변조왜곡 성분이 10 dB 이상 억제되었고, 상대강도잡음은 1.5 dB 이상 억제되었다. 2.3 GHz 에서 3 차 상호변조왜곡성분이 21.3 dB, SFDR 이 7.11 dB 향상된 결과를 얻었다. 또한 단일 모드 광섬유 전송 실험을 통해 전송길이에 따른 3 차 상호변호 왜곡성분의 크기 변화를 확인하였다.

• Journal of the Korea Institute of Military Science and Technology
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• v.9 no.3
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• pp.116-122
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• 2006

A fast scan digital-IF FFT receiver at the radio communication band is presented for spectrum monitoring applications. It is composed of three parts: RF front-end, fast LO board, and signal processing board. It has about 19GHz/s scan rate, multi frequency resolution from 10kHz to 2.5kHz, and high sensitivity of below -99dBm. The design and performance analysis of the digital-IF FFT receiver are presented.