• Proceedings of the Korean Information Science Society Conference
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• 2003.04d
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• pp.319-321
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• 2003

IMT2000다음으로 개방형 구조를 갖는 차세대 통신 시스템(SDR: Software Defined Radio)에 적용할 수 있는 정보보안 메커니즘으로 블록암호화 알고리즘인 'SEEO'를 구현하였다. SDR의 플랫폼은 주로 프로그래머블(Progammable)한 FPGA가 DSP가 주를 이루는데. 본 논문은 이러한 SDR 시스템 대상으로 적용할 수 있는, 한국형 블록 암호 알고리즘인 'SEED'를 DSP, FPGA로 구현하고 성능비교. 분석을 통하여 효과적이고 합리적인 SDR 암호화 모듈 구현의 방향을 모색해 보았다.

• Journal of the Korea Computer Industry Society
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• v.10 no.3
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• pp.105-114
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• 2009

In this paper a modified Feistel network 128 bit block cipher algorithm is proposed. The proposed algorithm has a 128, 196 or 256 bit key and it updates a selected 32 bit word from input value whole by deformed Feistel Network structure. Existing of such structural special quality is getting into block cipher algorithms and big distinction. The proposed block cipher algorithm shows much improved software speed compared with international standard block cipher algorithm AES and domestic standard block cipher algorithm SEED and ARIA. It may be utilized much in same field coming smart card that must perform in limited environment if use these special quality.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.14 no.5
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• pp.37-47
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• 2004

The security of personal informations has been an important issue since the field of smart card applications has been expanded explosively. The security of smart card is based on cryptographic algorithms, which are highly required to be implemented into hardware for higher speed and stronger security. In this paper, a SEED cryptographic processor is designed by employing one round key generation block which generates 16 round keys without key registers and one round function block which is used iteratively. Both the round key generation block and the F function are using only one G function block with one 5${\times}$l MUX sequentially instead of 5 G function blocks. The proposed SEED processor has been implemented such that each round operation is divided into seven sub-rounds and each sub-round is executed per clock. Functional simulation of the proposed cryptographic processor has been executed using the test vectors which are offered by Korea Information Security Agency. In addition, we have evaluated the proposed SEED processor by executing VHDL synthesis and FPGA board test. The die area of the proposed SEED processor decreases up to approximately 40% compared with the conventional processor.

• Journal of KIISE:Databases
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• v.41 no.4
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• pp.217-225
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• 2014

Analysis of social media such as Twitter can yield interesting perspectives to understanding human behavior, detecting hot issues, identifying influential people, or discovering a group and community. However, it is difficult to gather the data relevant to specific topics due to the main characteristics of social media data; data is large, noisy, and dynamic. This paper proposes a new algorithm that dynamically selects the seed nodes to efficiently collect tweets relevant to topics. The algorithm utilizes attributes of users to evaluate the user influence, and dynamically selects the seed nodes during the collection process. We evaluate the proposed algorithm with real tweet data, and get satisfactory performance results.

• Proceedings of the Korea Contents Association Conference
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• 2005.05a
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• pp.107-111
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• 2005

As Internet grows rapidly and next electronic commerce applications increase, the security is getting more important. Information security to provide secure and reliable information transfer is based on cryptography technique. The proposed ISEED(Improved SEED) algorithm based on block cryptography algorithm which belongs to secret-key algorithm. In terms of efficiency, the round key generation algorithm has been proposed to reduces the time required in encryption and decryption. The algorithm has been implemented as follow. 128-bit key is divided into two 64-bit group to rotate each of them 8-bit on the left side and right side, and then basic arithmetic operation and G function have been applied to 4-word outputs. In the process of converting encryption key which is required in decryption and encryption of key generation algorithm into sub key type, the conversion algorithm is analyzed. As a result, the time consumed to encryption and decryption is reduced by minimizing the number of plain text required differential analysis.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.41 no.10
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• pp.1244-1246
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• 2016

Influence maximization problem is to select seed node set, which maximizes information spread in social networks. Greedy algorithm shows an optimum solution, but has a high computational cost. A few heuristic algorithms were proposed to reduce the complexity, but their performance in influence maximization is limited. In this paper, we propose general degree discount algorithm, and show that it has better performance while keeping complexity low.

• Journal of KIISE:Computer Systems and Theory
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• v.31 no.7
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• pp.402-413
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• 2004

This paper presents an Implementation of Korean standard 128-bit block cipher SEED for the small (8 or 16-bits) embedded system using a low-cost FPGA(Field Programmable Gate Array) chip. Due to their limited computing and storage capacities most of the 8-bits/16-bits small embedded systems require a separate and dedicated cryptography processor for data encryption and decryption process which require relatively heavy computation job. So, in order to integrate the SEED with other logic circuit block in a single chip we need to invent a design which minimizes the area demand while maintaining the proper performance. But, the straight-forward mapping of the SEED specification into hardware design results in exceedingly large circuit area for a low-cost FPGA capacity. Therefore, in this paper we present a design which maximize the resource sharing and utilizing the modern FPGA features to reduce the area demand resulting in the successful implementation of the SEED plus interface logic with single low-cost FPGA. We achieved 66% area accupation by our SEED design for the XC2S100 (a Spartan-II series FPGA from Xilinx) and data throughput more than 66Mbps. This Performance is sufficient for the small scale embedded system while achieving tight area requirement.

• Journal of the Korea Society of Computer and Information
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• v.8 no.2
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• pp.112-121
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• 2003

Information Protection and cryptography technology is developed with if but solved problem of real time processing and secret maintain. Therefore this paper is Proposed new PRN-SEED(Pseudo-Random Number-SEED) for the increasing secret rate and processing rate perform performance analysis with existed other cryptography algorithms. Proposed new PRN-SEED crypto-algorithm increase in the processing rate than existed algorithms use bit and byte mixed operation with RNG(Random Number Generator). PRN-SEED that performs simultaneous operations have higher 1.03 in the processing rate and 2 in the cryptosystem performance than existed cryptosystems. Implementation for PRN-SEED use Synopsys Design Analyser Ver. 1999.10, samsung KG75 library and Synopsys VHDL Debegger. As a simulation result, symmetric cryptosystem DES operate 416Mbps at the 40MHz and Rijndael operate 612Mbps at the 50MHz. PRN-SEED cryptosystem have gate counting 10K and operate 430Mbps at the 40MHz and 630Mbps at the 50MHz.

• TTA Journal
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• s.65
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• pp.41-49
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• 1999

• TTA Journal
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• s.92
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• pp.46-50
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• 2004