• Journal of the Institute of Electronics Engineers of Korea TC
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• v.44 no.1
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• pp.69-78
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• 2007

A Frequency synthesizer for T-DMB and mobile-DTV applications was designed using $0.18{\mu}m$ CMOS process with 1.8V supply. PMOS transistors were chosen for VCO core to reduce phase noise. The VCO range is 920MHz-2100MHz using switchable inductors, capacitors and varactors. Varactor biases that improve varactor acitance characteristics were minimized as two, and $K_{VCO}$(VCO gain) value was aintained by switchable varactor. Additionally, VCO was designed that VCO gain and the interval of VCO gain were maintained using VCO gain compensation logic. VCO, PFD, CP and LF were verified by Cadence Spectre, and divider was simulated using Matlab Simulink, ModelSim and HSPICE. VCO consumes 10mW power, and is 56.3% tuning range. VCO phase noise is -127dBc/Hz at 1MHz offset for 1.58GHz output frequency. Total power consumption of the frequency synthesizer is 18mW, and lock time is about $140{\mu}s$.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.13 no.11
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• pp.914-920
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• 2000

When the charge-trap type SONOS(polysilicon-oxide-nitride-oxide-semiconductor) cells are used to flash memory, the tunneling program/erase condition to minimize the generation of interface traps was investigated. SONOSFET NVSM(Nonvolatile Semiconductor Memory) cells were fabricated using 0.35 ㎛ standard memory cell embedded logic process including the ONO cell process, based on retrograde twin-well, single-poly, single metal CMOS(Complementary Metal Oxide Semiconductor) process. The thickness of ONO triple-dielectric for the memory cell is tunnel oxide of 24 $\AA$, nitride of 74 $\AA$, blocking oxide of 25 $\AA$, respectively. The program mode(V$\_$g/=7, 8, 9 V, V$\_$s/=V$\_$d/=-3 V, V$\_$b/=floating) and the erase mode(V$\_$g/=-4, -5, -6 V, V$\_$s/=V$\_$d/=floating, V$\_$b/=3 V) by MFN(Modified Fowler-Nordheim) tunneling were used. The proposed programming condition for the flash memory of SONOSFET NVSM cells showed less degradation(ΔV$\_$th/, S, G$\_$m/) characteristics than channel MFN tunneling operation. Also, the program inhibit conditins of unselected cell for separated source lines NOR-type flash memory application were investigated. we demonstrated that the phenomenon of the program disturb did not occur at source/drain voltage of 1 V∼12 V and gate voltage of -8 V∼4 V.

• Journal of the Korean Society for Precision Engineering
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• v.16 no.8
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• pp.193-202
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• 1999

Crane operation for transporting heavy loads causes swinging motion at the loads due to crane's acceleration and deceleration. This sway causes the suspension ropes to leave their grooves and leads to possibility of serious damages. So, this swing of the objects is a serious problem and the goal of crane system is transporting to a goal position as soon as possible without the oscillation of the rope. Generally crane is operated by expert's knowledge. Therefore, a satisfactory control method to supress object sway during transport is indispensible. The dynamic behavior of the crane shows nonlinear characteristics. when the length of the rope is changed the crane is time varying system and the design of anti-sway controller is very difficult. In this paper, the nonlinear dynamic model for the industrial overhead crane whose girder, trolley and hoister move simultaneously is derived. and the Fuzzy logic controller based on the expert experiments during acceleration, constant velocity, deceleration and stop position period is proposed to supress the swing motion and control the position of the crane. The performance of the fuzzy controller for the nonlinear crane model is simulated on the personal computer.

• Transactions of the Korean Society of Automotive Engineers
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• v.18 no.4
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• pp.8-17
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• 2010

In this paper, a fault tolerant control against sensor faults of electric parking brake (EPB) is proposed. Fault tolerant control method of EPB system is strongly demanded since sensor faults can endanger a driver's safety. In this paper, a clamp force estimation method is presented using motor's armature current and angular velocity. Clamp force estimation method is applied for fault detection method with parity equations. The goal of the detection method is to detect and identify faults in encoder, current sensor, force sensor, and parking cable. And a switching logic for fault tolerant control against the three sensor faults is suggested. Experimental results show that the proposed force estimation method satisfies the specifications of EPB system. The effectiveness of the fault detection method is validated with experimental results. Although a single sensor fault happens, EPB system with the proposed fault detection method does not develop into a failure on subsystem or system level.

• Proceedings of the KIEE Conference
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• 1997.07c
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• pp.1006-1008
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• 1997

This paper presents the logic based High Impedance Fault(HIF) detection rules for distribution lines. Due to the characteristics of HIF, which shows low current on relaying points, it is difficult to detect the fault occurred in distribution line by the conventional overcurrent relay(OCR) and/or harmonics relay. The HIF data were generated by using TACS in EMTP. In this paper, The harmonic index is defined as the ratio of harmonic component to fundamental component. The proposed HIF detection rules are obtained by analysing the difference between normal condition and HIF condition.

• Progress in Superconductivity and Cryogenics
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• v.23 no.4
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• pp.56-60
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• 2021

The microwave Radar used for special purposes in the past is being applied in various areas due to the technological advancement and cost reduction, and is particularly applied to autonomous driving in the automobile field. The FMCW (Frequency Modulated Continuous Wave) Radar can acquire level information of liquid in vessel based on the beat frequency obtained by continuously transmitting and receiving signals by modulating the frequency over time. However, for cryogenic fluids with small impedance differences between liquid medium and gas medium, such as liquid nitrogen and liquid hydrogen, it is difficult to apply a typical Radar-based level meter. In this study, we develop an 80 GHz FMCW Radar for level measurement of cryogenic fluids with small impedance differences between media and analyze its characteristics. Here, because of the low intrinsic impedance difference, most of the transmitted signal passes through the liquid nitrogen interface and is reflected at the bottom of the vessel. To solve this problem, a radar measurement algorithm was designed to detect multiple targets and separate the distance signal to the bottom of the vessel in order to estimate the precise position on the liquid nitrogen interface. Thereafter, performance verification experiments were performed according to the liquid nitrogen level using the developed radar level meter.

• The KIPS Transactions:PartD
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• v.12D no.7 s.103
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• pp.947-956
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• 2005

Software(S/W) reengineering is one of the effective technologies to produce a business worth and en and the S/W ROI continuously. In spite of, S/W reengineering has been recognized a cost-consumptive works with inefficient productivity. In fact we have used to transform to confusion system with destructive system architecture by extending and updating legacy system in a temporary expedients. Moreover it is impossible to provide the time-market products for coping with rapid changeable system environment and meeting to complicated customer's requirements. Therefore, we need a systematic reengineering methodology to fulfill the changeable environment, as appearance of new IT techniques, various alteration of business information model, and increment of business logic. Legacy systems can be utilized as the core property in business organization through reengineering methodology. In this paper, we target to establish the reengineering process, proposed MaRMI-RE consisting of initial Planning phase, reverse engineering and component transformation phase. To describe the MaRMI-RE, we presented the concrete tasks and techniques and artifacts per individual phase in process, and the case study is showed briefly.

• Proceedings of the KIEE Conference
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• 2015.07a
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• pp.818-819
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• 2015

PAL-XFEL 장치에 사용 할 고전압 펄스 모듈레이터 출력파워는 수 ${\mu}s$ 범위의 짧은 고전압(400 kV), 대전류(500 A) 펄스를 요구한다. 이러한 펄스파워를 얻기 위해서 PFN(Pulse Forming Network)에 에너지를 축적하고, 플라즈마 스위치인 싸이라트론을 통하여 에너지를 신속하게 클라이스트론 쪽으로 전달한다. 클라이스트론은 모듈레이터에서 공급하는 펄스 전원을 이용하여 RF를 증폭하는 대출력 고주파 증폭장치이다. 고전압 펄스 모듈레이터 제어기는 고속펄스 신호처리 모듈(Fast Pulse Signal Conditioning Module), PLC(Programmable Logic Controller)로 구성되어 있다. 고전압 펄스 모듈레이터에 사용하는 대용량 싸이라트론은 고전력을 스위칭 할 때 발생하는 스위칭 노이즈는 매우 크다. 이러한 노이즈는 모듈레이터의 출력 시그널인 빔 전압, 빔 전류, EOLC(End of Line Clipper) 전류, DC high voltage에 섞여 있으면서 신호 왜곡 및 제어장치의 고장을 유발시킨다. 이처럼 노이즈가 많이 포함되어 있는 아닐로그 신호를 깨끗한 신호(a clean signal)로 바꾸어주는 노이즈 필터링 장치인 고속펄스 신호처리 모듈을 제작하여 실험한 결과를 알아보고 모듈레이터 인터록 시스템인 PLC에서 Dynamic Interlock의 응답시간을 빠르게 하기위한 회로 수정에 대한 결과에 관하여 기술하고자 한다.

• Journal for History of Mathematics
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• v.24 no.3
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• pp.37-58
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• 2011

The development of recent Mathematical Logic is mostly originated in Hilbert's Proof Theory. The purpose of the plan so called Hilbert's Program lies in the formalization of mathematics by formal axiomatic method, rescuing classical mathematics by means of verifying completeness and consistency of the formal system and solidifying the foundations of mathematics. In 1931, the completeness encounters crisis by the existence of undecidable proposition through the 1st Theorem of G?del, and the establishment of consistency faces a risk of invalidation by the 2nd Theorem. However, relative of partial realization of Hilbert's Program still exists as a fruitful research program. We have tried to bring into relief through Curry-Howard Correspondence the fact that Hilbert's program serves as source of power for the growth of mathematical constructivism today. That proof in natural deduction is in truth equivalent to computer program has allowed the formalization of mathematics to be seen in new light. In other words, Hilbert's program conforms best to the concept of algorithm, the central idea in computer science.

• The Journal of the Acoustical Society of Korea
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• v.18 no.2
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• pp.53-60
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• 1999

In this paper, it is proposed to a new architecture of CMOS IADC(Current-Mode Analog-to-Digital Converter) using 1.5-bit bit cell of which consists a CSH(Current-Mode Sample-and-Hold) and CCMP(Current-Mode Comparator). In order to guarantee the entire linearity of IADC, the CSH is designed to cancel CFT(Clock Feedthrough) whose resolution is to meet at the least 9-bit which is placed in the front-end of each bit cell. In the proposed IADC, digital correction logic is simplified and power consumption is reduced because bit cell of each stage needs two latch CCMP. Also, it is available for a mixed-mode integrated circuit because all of block is designed with only MOS transistor. With the HYUNDAI 0.8㎛ CMOS parameter, the HSPICE simulation results show that the proposed IADC can be operated at 20Ms/s with SNR of 43 dB with which is satisfied 7-bit resolution for input signal at 100 ㎑, and its power consumption is 27㎽.