• Proceedings of the KIEE Conference
• /
• 1996.07b
• /
• pp.974-976
• /
• 1996

In this paper, a reference model following control system using a fuzzy logic controller(FLC) is proposed By using an integrator and a nonlinear hysteresis element, a reference model whose response has no overshoot and fast rise time is designed. A FLC is designed to follow as close as possible to the response of the reference model. The proposed design method is shown that the robustness and the optimal tracking property can be achieved under modeling error, disturbance and parameter perturbations. The effectiveness of the proposed design method is verified through the simulation that compare using the FLC with using a $H_{\infty}$ controller.

• Proceedings of the KIEE Conference
• /
• 2007.07a
• /
• pp.1756-1757
• /
• 2007

어느 정도 규모를 가진 실험 설비를 자동화하기 위해서 분산 I/O를 지원해 주는 자동화 컨트롤러를 사용하는 것이 편리하며 이러한 용도로 PLC(Programmable Logic Controller), PAC(Programmable Automation Controller) 등을 사용하고 있다. 하지만 기능적으로 필요로 하는 I/O 이외에 전원장치, 백프레임, 그리고 메인콘트롤러 등의 항목이 추가된다. 이러한 제한은 필요로 하는 자동화 대상인 설비의 I/O의 접점수가 많지 않지만 이들을 분산하여 설치될 필요가 있을 경우 전체 시스템을 자동화 하는데 소요되는 비용을 필요 이상으로 높이게 된다. 본 연구는 현재 한국원자력연구원에서 시험 운전 중인 TS-NBI 장치의 자동화에 이용할 목적으로 자동화 대상 설비의 I/O 접점수가 많지 않지만 분산 I/O로 구성하여야 하는 경우에 적용할 해결책을 찾기 위해서 수행 하였다.

• Journal of the Korean Association of Geographic Information Studies
• /
• v.23 no.4
• /
• pp.1-15
• /
• 2020

As cities expand and underground utilities construction projects increase, there is an urgent need for a technology capable of analyzing the underground utilities network in 3D. Since 2015, 3D Underground Geospatial Map project, that has been integrating 15 types of underground information such as underground utilities, underground structures, and ground information, is in progress in S. Korea. However, the construction of 3D underground facilities is currently based on manual work and the logic for building a 3D model is very complicated. And it takes a lot of time and cost to process millions of large amounts of data per local governments. By presenting a framework on the processing and partial updating of the 3D underground utilities model, this paper aims to establish a plan to quickly build a 3D underground utility model at a minimum cost. The underground utilities processing and partial update automation technologies developed in this study are expected to be immediately applied to the 3D Underground Geospatial Map project.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
• /
• v.16 no.6
• /
• pp.454-464
• /
• 2023

This paper proposes a low-power 8-bit asynchronous SAR ADC with a sampling rate of 1 MS/s for sensor node applications. The ADC uses bootstrapped switches to improve linearity and applies a VCM-based CDAC switching technique to reduce the power consumption and area of the DAC. Conventional synchronous SAR ADCs that operate in synchronization with an external clock suffer from high power consumption due to the use of a clock faster than the sampling rate, which can be overcome by using an asynchronous SAR ADC structure that handles internal comparisons in an asynchronous manner. In addition, the SAR logic is designed using dynamic logic circuits to reduce the large digital power consumption that occurs in low resolution ADC designs. The proposed ADC was simulated in a 180-nm CMOS process, and at a 1.8 V supply voltage and a sampling rate of 1 MS/s, it consumed 46.06 𝜇W of power, achieved an SNDR of 49.76 dB and an ENOB of 7.9738 bits, and obtained a FoM of 183.2 fJ/conv-step. The simulated DNL and INL are +0.186/-0.157 LSB and +0.111/-0.169 LSB.

• Proceedings of the Korea Information Processing Society Conference
• /
• 2005.05a
• /
• pp.1765-1768
• /
• 2005

Binary-search 알고리즘을 이용한 새로운 6-bit 300MS/s ADC 를 제안 하였다. 본 연구에서 제안된 ADC 는 저전력, 고속동작, 저해상도의 응용분야에 적합하도록 설계 되었다. 11 개의 rail-to-rail 비교기와 기준전압 발생기, 그리고 기준전압 제어회로로 구성 되었으며, 이는 기존의 구조와는 다른 전혀 새로운 형태로 제안된 것이다. 전력소모를 줄이기 위해 비교기 공유기술을 사용하였다. 또한 ADC 의 sub-block 인 rail-to-rail 비교기는 인버터 logic threshold 전압 값을 이용한 새로운 형태의 비교기를 제안하였다. 비교기는 인버터와 n-type preamp, p-type preamp 그리고 각각에 연결되는 latch 로 구성되었다. 기존의 rail-to-rail comparator 에 비해 입력 범위 전체 영역에서 일정한 gm 값을 얻을 수 있다. 실험결과 2.5V 공급전압에서, 17mW 의 전력 소모를 보이며, 최대 304MS/s 의 데이터 변환율을 가진다. INL 과 DNL 은 입력신호가 2.38Mhz 의 주파수를 가지는 삼각파일 때, 각각 ${\pm}0.54LSB$, ${\pm}1LSB$ 보다 작다. TSMC 0.25u 공정을 이용하였다.

• Journal of the Korean Institute of Telematics and Electronics A
• /
• v.33A no.4
• /
• pp.152-161
• /
• 1996

In tis work, a three-stage pipelined A/D converter (ADC) was implemented to obtain 10-bit resolution at a conversion rate of 20 msamples/s for video applications. The ADC consists of three identical stages employing a mid-rise coding technique. The interstage errors such as offsets and clock feedthrough are digitally corrected in digitral logic by one overlapped bit between stages. The proposed ADC is optimized by adopting a unit-capacitor array architecture in the MDAC to improve the differential nonlinearity and the yield. Reduced power dissipation has been achieve dby using low-power latched comparators. The prototype was fabricated in a 0.8$\mu$m p-well CMOS technology. The ADC dissipates 160 mW at a 20 MHz clock rate with a 5 V single supply voltage and occupies a die area of 7 mm$^{2}$(2.7 mm $\times$ 2.6mm) including bonding pads and stand-alone internal bias circuit. The typical differential and integral nonlinarities of the prototype are less than $\pm$ 0.6 LSB and $\pm$ 1 LSB, respectively.

• Journal of the Institute of Electronics and Information Engineers
• /
• v.53 no.7
• /
• pp.17-26
• /
• 2016

This work proposes a 12b 60MS/s 0.18um CMOS Flash-SAR ADC for various systems such as wireless communications and portable video processing systems. The proposed Flash-SAR ADC alleviates the weakness of a conventional SAR ADC that the operation speed proportionally increases with a resolution by deciding upper 4bits first with a high-speed flash ADC before deciding lower 9bits with a low-power SAR ADC. The proposed ADC removes a sampling-time mismatch by using the C-R DAC in the SAR ADC as the combined sampling network instead of a T/H circuit which restricts a high speed operation. An interpolation technique implemented in the flash ADC halves the required number of pre-amplifiers, while a switched-bias power reduction scheme minimizes the power consumption of the flash ADC during the SAR operation. The TSPC based D-flip flop in the SAR logic for high-speed operation reduces the propagation delay by 55% and the required number of transistors by half compared to the conventional static D-flip flop. The prototype ADC in a 0.18um CMOS demonstrates a measured DNL and INL within 1.33LSB and 1.90LSB, with a maximum SNDR and SFDR of 58.27dB and 69.29dB at 60MS/s, respectively. The ADC occupies an active die area of $0.54mm^2$ and consumes 5.4mW at a 1.8V supply.

• Journal of the Microelectronics and Packaging Society
• /
• v.22 no.2
• /
• pp.11-19
• /
• 2015

Since CMOS device scaling has stalled, three-dimensional (3-D) integration allows extending Moore's law to ever high density, higher functionality, higher performance, and more diversed materials and devices to be integrated with lower cost. 3-D integration has many benefits such as increased multi-functionality, increased performance, increased data bandwidth, reduced power, small form factor, reduced packaging volume, because it vertically stacks multiple materials, technologies, and functional components such as processor, memory, sensors, logic, analog, and power ICs into one stacked chip. Anticipated applications start with memory, handheld devices, and high-performance computers and especially extend to multifunctional convengence systems such as cloud networking for internet of things, exascale computing for big data server, electrical vehicle system for future automotive, radioactivity safety system, energy harvesting system and, wireless implantable medical system by flexible heterogeneous integrations involving CMOS, MEMS, sensors and photonic circuits. However, heterogeneous integration of different functional devices has many technical challenges owing to various types of size, thickness, and substrate of different functional devices, because they were fabricated by different technologies. This paper describes new 3-D heterogeneous integration technologies of chip self-assembling stacking and 3-D heterogeneous opto-electronics integration, backside TSV fabrication developed by Tohoku University for multifunctional convergence systems. The paper introduce a high speed sensing, highly parallel processing image sensor system comprising a 3-D stacked image sensor with extremely fast signal sensing and processing speed and a 3-D stacked microprocessor with a self-test and self-repair function for autonomous driving assist fabricated by 3-D heterogeneous integration technologies.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.29 no.11A
• /
• pp.1271-1277
• /
• 2004

We propose a foe phase tuner and a rounding processor for a numerically controlled oscillator (NCO), yielding a reduced phase error in generating a digital sine waveform. By using the fine Phase tuner Presented in this paper, when the ratio of the desired sine wave frequency to the clock frequency is expressed as a fraction, an accurate adjustment in representing the fractional value can be achieved with simple hardware. In addition, the proposed rounding processor reduces the effects of phase truncation on the output spectrum. Logic simulation results of the NCO for multi-carrier channel separation in cdma2000 3X multi-carrier receive system using these techniques show that the noise spectrum and mean square error (MSE) are reduced by 8.68 dB and 5.5 dB, respectively compared to those of truncation method and 2.38 dB and 0.83 dB, respectively, compared to those of Paul's scheme.

• Journal of Korea Technology Innovation Society
• /
• v.15 no.4
• /
• pp.815-836
• /
• 2012

Corporate Laboratories have been a key driver of Korea's economic growth through attaining technology competitiveness. The study is focused on selecting outstanding small and medium corporate laboratories with high R&D capability and fostering the selected laboratories. The main topics of this study are to establish logics regarding the selection process and to propose the implementation schemes of the process. For the selection of outstanding laboratories, this study presents a evaluation indicators based on logic model and verification of the validity of following evaluation indicators through a Pilot test. The evaluation indicators from this study are expected to be in practical use as a reference for support policies of outstanding laboratories' R&D activities. For corporations, these indicators can be used to examine their R&D capability. This study also suggests differentiated policy support measures using the findings to maximize the effectiveness of the selection process.