• JSTS:Journal of Semiconductor Technology and Science
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• 제12권1호
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• pp.1-9
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• 2012

A 10-b 500 MS/s A/D converter (ADC) with a hybrid calibration and error correction logic is described. The ADC employs a single-channel cascaded folding-interpolating architecture whose folding rate (FR) is 25 and interpolation rate (IR) is 8. To overcome the disadvantage of an offset error, we propose a hybrid self-calibration circuit at the open-loop amplifier. Further, a novel prevision digital error correction logic (DCL) for the folding ADC is also proposed. The ADC prototype using a 130 nm 1P6M CMOS has a DNL of ${\pm}0.8$ LSB and an INL of ${\pm}1.0$ LSB. The measured SNDR is 52.34-dB and SFDR is 62.04-dBc when the input frequency is 78.15 MHz at 500 MS/s conversion rate. The SNDR of the ADC is 7-dB higher than the same circuit without the proposed calibration. The effective chip area is $1.55mm^2$, and the power dissipates 300 mW including peripheral circuits, at a 1.2/1.5 V power supply.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2006년도 하계종합학술대회
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• pp.659-660
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• 2006

The low crosstalk row-decoder is studied for PoRAM applications. Because polymer-based memories can be more densely integrated than established silicon-based ones, PoRAM is highly sensitive for the crosstalk problem. To overcome the problem and to suggest the suitable decoder for PoRAM, this paper shows the comparison of the row-path characteristics for both the 2-stage dynamic logic decoder and the 2-stage static logic decoder. Moreover, to suppress the Glitch effect which is observed by using the static logic decoder, the Master-Slave(M/S) D-Flip/Flop(D-F/F) is applied as a deglitch. Finally, the improved output result of the 2-stage static logic decoder with the M/S D-F/F is shown..

• 정보처리학회논문지A
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• 제15A권3호
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• pp.135-140
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• 2008

본 논문은 중복 다치논리(redundant multi-valued logic)를 이용하여 초고속 디멀티플렉서(demultiplexer)를 CMOS 회로로 설계하였다. 설계한 회로는 중복 다치논리를 이용하여 직렬 이진 데이터를 병렬 다치 데이터로 변환하고 이를 다시 병렬 이진 데이터로 변환한다. 중복 다치논리는 중복된 다치 데이터 변환으로써 기존 방식 보다 더 높은 동작속도를 얻을 수 있다. 구현한 디멀티플렉서는 8개의 적분기로 구성되어 있으며, 각 적분기는 누적기, 비교기, 디코더, D 플립플롭으로 구성된다. 설계한 회로는 0.18um 표준 CMOS 공정으로 구현하였으며 HSPICE 시뮬레이션을 통해 검증하였다. 본 논문의 디멀티플렉서의 최대 데이터 전송률은 20 Gb/s이고 평균 전력소모는 58.5 mW이다.

• 정보처리학회논문지:컴퓨터 및 통신 시스템
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• 제11권9호
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• pp.289-304
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• 2022

스마트 IoT의 특징인 분산성 및 이동성에 기반한 안전 요구사항을 분석 및 검증하기 위한 프로세스 대수 및 논리가 요구된다. 하지만 기존의 프로세스 대수 및 논리는 분산성 및 이동성에 대한 표현이 제한적이므로 스마트 IoT의 요구사항 분석 및 검증이 비직관적이다. 이러한 한계를 극복하기 위해, 본 논문에서는 GTS-VL(Geo-Temporal Space-Visual Logic)을 제시한다. GTS-VL은 GTS에서 표현된 블록 간의 관계를 다루는 1차술어논리이며, GTS는 프로세스 대수인 dTP-Calculus를 사용하여 명세한 시스템의 동작 과정을 2차원 시공간에서 표현한 그래프이다. 본 논문에서 사용한 SAVE 도구는 ADOxx Meta-modeling Platform을 통해 개발되었으며, SAVE를 사용하여 PBC(Producer-Buffer-Consumer) 예제의 안전 요구사항을 분석 및 검증하고 문자 및 시각화 기반 검증 방법을 비교 분석하여 장점 및 실용성을 보인다.

• 한국발생생물학회지:발생과생식
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• 제26권4호
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• pp.183-190
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• 2022

Today's Eastern philosophers try to use the formal logic organized by Aristotle, saying that there was no logic in the East. This researcher found that Confucius and other Asians used Che-Yong logic. The Che-Yong logic is based on the Che-Yong law, which is a natural law. The Che-Yong law consists of the Che-Yong principle and the Hyeon-Mi principle. The Hyeon-Mi principle is that if there is an appearance on the outside, there is a corresponding cause in it. The Che-Yong principle is that the highest common cause of various appearances is Che, and the Che grows and changes on its own to become a Yong. Identifying Che and predicting Yong is Che-Yong logic. Here, I'd like to introduce Che-Yong logic and suggest a new research methodology to apply it.

• 전기학회논문지
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• 제67권6호
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• pp.745-752
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• 2018

ICs(Integrated circuits) for nuclear power plant exposed to radiation environment occur malfunctions and data errors by the TID(Total ionizing dose) effects among radiation-damage phenomenons. In order to protect ICs from the TID effects, this paper proposes a radiation-hardening of the logic circuit(D-latch) which used for the data synchronization and the clock division in the ICs design. The radiation-hardening technology in the logic device(NAND) that constitutes the proposed RH(Radiation-hardened) D-latch is structurally more advantageous than the conventional technologies in that it keeps the device characteristics of the commercial process. Because of this, the unit cell based design of the RH logic device is possible, which makes it easier to design RH ICs, including digital logic circuits, and reduce the time and cost required in RH circuit design. In this paper, we design and modeling the structure of RH D-latch based on commercial $0.35{\mu}m$ CMOS process using Silvaco's TCAD 3D tool. As a result of verifying the radiation characteristics by applying the radiation-damage M&S (Modeling&Simulation) technique, we have confirmed the radiation-damage of the standard D-latch and the RH performance of the proposed D-latch by the TID effects.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1992년도 하계학술대회 논문집 A
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• pp.225-230
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• 1992

In this paper, a new learning fuzzy logic controller(LFLC) is presented. The proposed controller is composed of the main control part and the learning part. The main control part is a fuzzy logic controller(FLC) based on linguistic rules and fuzzy inference. For the learning part, artificial neural network(ANN) is added to FLC so that the controller may adapt to unknown plant and environment. According to the output values of the ANN part, which is learned using error back-propagation algorithm, scale factors of the FLC part are determined. These scale factors transfer the range of values of input variables into corresponding universe of discourse in the FLC part in order to achieve good performance. The effectiveness of the proposed control strategy has been demonstrated through simulations involving the control of an unknown robot manipulator with load disturbance.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1999년도 하계학술대회 논문집 G
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• pp.3215-3217
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• 1999

In this paper, a new structure of realizing switching control logic for Data Weighted Average Technique is suggested. It uses memory and adder for summing past binary input and this summed data is used to select one switch in control logic. This control logic acts in parallel regardless of resolution so increasing resolution don't affect on converting speed. In this reason, high speed and high resolution D/A converter based on Data Weighted Average Technique could be made. In this paper, 4 bits current mode thermometer code D/A converter is degined and simulated by using HSPICE. Simulated results show that new structure of D/A converter has more than 250MHz converting speed and less than 0.0003[LSB] INL error. It is very useful in low power circuit because of using 3.3 V supply voltage.

• Journal of the Optical Society of Korea
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• 제16권1호
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• pp.13-16
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• 2012

We demonstrate an optical gate architecture using a single SOA to perform AND, OR and NOT logic functions. Simple reconfigurable all-optical logic operations are implemented using RZ modulated signals at 40 Gb/s. Contrast ratio and extinction ratio values have been analysed for the different types of logic gates. Maximum extinction ratio and contrast ratio achieved are 19dB and 17.2 dB respectively. Simple structure and potential for integration makes this architecture an interesting approach in photonic computing and optical signal processing.

• 한국원자력학회:학술대회논문집
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• 한국원자력학회 1996년도 추계학술발표회논문집(1)
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• pp.191-196
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• 1996

The potential value of the Application Specific Integrated Circuits(ASIC's) in safety systems of Nuclear Power Plants(NPP's) is being increasingly recognized because they are essentially hardwired circuitry on a chip, the reliability of the system can be proved more easily than that of software based systems which is difficult in point of software V&V(Verification and Validation). There are two types of ASIC, one is a full customized type, the other is a half customized type. PLD(Programmable Logic Device) used in this paper is a half customized ASIC which is a device consisting of blocks of logic connected with programmable interconnections that are customized in the package by end users. This paper describes the RPS(Reactor Protection System) composed of ASICs which provides emergency shutdown of the reactor to protect the core and the pressure boundary of RCS(Reactor Coolant System) in NPP's. The RPS is largely composed of five logic blocks, each of them was implemented in one PLD, as the followings. A). Bistable Logic B). Matrix Logic C).Initiation Logic D). MMI(Man Machine Interface) Logic E). Test Logic.