• JSTS:Journal of Semiconductor Technology and Science
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• v.12 no.1
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• pp.1-9
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• 2012

A 10-b 500 MS/s A/D converter (ADC) with a hybrid calibration and error correction logic is described. The ADC employs a single-channel cascaded folding-interpolating architecture whose folding rate (FR) is 25 and interpolation rate (IR) is 8. To overcome the disadvantage of an offset error, we propose a hybrid self-calibration circuit at the open-loop amplifier. Further, a novel prevision digital error correction logic (DCL) for the folding ADC is also proposed. The ADC prototype using a 130 nm 1P6M CMOS has a DNL of ${\pm}0.8$ LSB and an INL of ${\pm}1.0$ LSB. The measured SNDR is 52.34-dB and SFDR is 62.04-dBc when the input frequency is 78.15 MHz at 500 MS/s conversion rate. The SNDR of the ADC is 7-dB higher than the same circuit without the proposed calibration. The effective chip area is $1.55mm^2$, and the power dissipates 300 mW including peripheral circuits, at a 1.2/1.5 V power supply.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.659-660
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• 2006

The low crosstalk row-decoder is studied for PoRAM applications. Because polymer-based memories can be more densely integrated than established silicon-based ones, PoRAM is highly sensitive for the crosstalk problem. To overcome the problem and to suggest the suitable decoder for PoRAM, this paper shows the comparison of the row-path characteristics for both the 2-stage dynamic logic decoder and the 2-stage static logic decoder. Moreover, to suppress the Glitch effect which is observed by using the static logic decoder, the Master-Slave(M/S) D-Flip/Flop(D-F/F) is applied as a deglitch. Finally, the improved output result of the 2-stage static logic decoder with the M/S D-F/F is shown..

• The KIPS Transactions:PartA
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• v.15A no.3
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• pp.135-140
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• 2008

This paper describes a high-speed CMOS demultiplexer using redundant multi-valued logic (RMVL). The proposed circuit receives serial binary data and is converted to parallel redundant multi-valued data using RMVL. The converted data are reconverted to parallel binary data. By the redundant multi-valued data conversion, the RMVL makes it possible to achieve higher operating speeds than that of a conventional binary logic. The implemented demultiplexer consists of eight integrators. Each integrator is composed of an accumulator, a window comparator, a decoder and a D flip flop. The demultiplexer is designed with TSMC $0.18{\mu}m$ standard CMOS process. The validity and effectiveness are verified through the HSPICE simulation. The demultiplexer is achieved the maximum data rate of 20 Gb/s and the average power consumption of 95.85 mW.

• KIPS Transactions on Computer and Communication Systems
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• v.11 no.9
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• pp.289-304
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• 2022

It is necessary to apply process algebra and logic in order to analyze and verify safety requirements for Smart IoT Systems due to distributivity and mobility of the systems over some predefined geo-temporal space. However the analysis and verification cannot be fully intuitive over the space due to the fact that the existing process algebra and logic are very limited to express the distributivity and the mobility. In order to overcome the limitations, the paper presents a new logic, namely for GTS-VL (Geo-Temporal Space-Visual Logic), visualization of the analysis and verification over the space. GTS-VL is the first order logic that deals with relations among the different types of blocks over the space, which is the graph that visualizes the system behaviors specified with the existing dTP-Calculus. A tool, called SAVE, was developed over the ADOxx Meta-Modeling Platform in order to demonstrate the feasibility of the approach, and the advantages and practicality of the approach was shown with the comparative analysis of PBC (Producer-Buffer-Consumer) example between the graphical analysis and verification method over the textual method with SAVE tool.

• Development and Reproduction
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• v.26 no.4
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• pp.183-190
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• 2022

Today's Eastern philosophers try to use the formal logic organized by Aristotle, saying that there was no logic in the East. This researcher found that Confucius and other Asians used Che-Yong logic. The Che-Yong logic is based on the Che-Yong law, which is a natural law. The Che-Yong law consists of the Che-Yong principle and the Hyeon-Mi principle. The Hyeon-Mi principle is that if there is an appearance on the outside, there is a corresponding cause in it. The Che-Yong principle is that the highest common cause of various appearances is Che, and the Che grows and changes on its own to become a Yong. Identifying Che and predicting Yong is Che-Yong logic. Here, I'd like to introduce Che-Yong logic and suggest a new research methodology to apply it.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.67 no.6
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• pp.745-752
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• 2018

ICs(Integrated circuits) for nuclear power plant exposed to radiation environment occur malfunctions and data errors by the TID(Total ionizing dose) effects among radiation-damage phenomenons. In order to protect ICs from the TID effects, this paper proposes a radiation-hardening of the logic circuit(D-latch) which used for the data synchronization and the clock division in the ICs design. The radiation-hardening technology in the logic device(NAND) that constitutes the proposed RH(Radiation-hardened) D-latch is structurally more advantageous than the conventional technologies in that it keeps the device characteristics of the commercial process. Because of this, the unit cell based design of the RH logic device is possible, which makes it easier to design RH ICs, including digital logic circuits, and reduce the time and cost required in RH circuit design. In this paper, we design and modeling the structure of RH D-latch based on commercial $0.35{\mu}m$ CMOS process using Silvaco's TCAD 3D tool. As a result of verifying the radiation characteristics by applying the radiation-damage M&S (Modeling&Simulation) technique, we have confirmed the radiation-damage of the standard D-latch and the RH performance of the proposed D-latch by the TID effects.

• Proceedings of the KIEE Conference
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• 1992.07a
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• pp.225-230
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• 1992

In this paper, a new learning fuzzy logic controller(LFLC) is presented. The proposed controller is composed of the main control part and the learning part. The main control part is a fuzzy logic controller(FLC) based on linguistic rules and fuzzy inference. For the learning part, artificial neural network(ANN) is added to FLC so that the controller may adapt to unknown plant and environment. According to the output values of the ANN part, which is learned using error back-propagation algorithm, scale factors of the FLC part are determined. These scale factors transfer the range of values of input variables into corresponding universe of discourse in the FLC part in order to achieve good performance. The effectiveness of the proposed control strategy has been demonstrated through simulations involving the control of an unknown robot manipulator with load disturbance.

• Proceedings of the KIEE Conference
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• 1999.07g
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• pp.3215-3217
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• 1999

In this paper, a new structure of realizing switching control logic for Data Weighted Average Technique is suggested. It uses memory and adder for summing past binary input and this summed data is used to select one switch in control logic. This control logic acts in parallel regardless of resolution so increasing resolution don't affect on converting speed. In this reason, high speed and high resolution D/A converter based on Data Weighted Average Technique could be made. In this paper, 4 bits current mode thermometer code D/A converter is degined and simulated by using HSPICE. Simulated results show that new structure of D/A converter has more than 250MHz converting speed and less than 0.0003[LSB] INL error. It is very useful in low power circuit because of using 3.3 V supply voltage.

• Journal of the Optical Society of Korea
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• v.16 no.1
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• pp.13-16
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• 2012

We demonstrate an optical gate architecture using a single SOA to perform AND, OR and NOT logic functions. Simple reconfigurable all-optical logic operations are implemented using RZ modulated signals at 40 Gb/s. Contrast ratio and extinction ratio values have been analysed for the different types of logic gates. Maximum extinction ratio and contrast ratio achieved are 19dB and 17.2 dB respectively. Simple structure and potential for integration makes this architecture an interesting approach in photonic computing and optical signal processing.

• Proceedings of the Korean Nuclear Society Conference
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• 1996.11a
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• pp.191-196
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• 1996

The potential value of the Application Specific Integrated Circuits(ASIC's) in safety systems of Nuclear Power Plants(NPP's) is being increasingly recognized because they are essentially hardwired circuitry on a chip, the reliability of the system can be proved more easily than that of software based systems which is difficult in point of software V&V(Verification and Validation). There are two types of ASIC, one is a full customized type, the other is a half customized type. PLD(Programmable Logic Device) used in this paper is a half customized ASIC which is a device consisting of blocks of logic connected with programmable interconnections that are customized in the package by end users. This paper describes the RPS(Reactor Protection System) composed of ASICs which provides emergency shutdown of the reactor to protect the core and the pressure boundary of RCS(Reactor Coolant System) in NPP's. The RPS is largely composed of five logic blocks, each of them was implemented in one PLD, as the followings. A). Bistable Logic B). Matrix Logic C).Initiation Logic D). MMI(Man Machine Interface) Logic E). Test Logic.