• The Journal of Korea Robotics Society
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• v.4 no.1
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• pp.68-73
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• 2009

The UPnP is middleware architecture that supports dynamic distributed computing environment. It has many good features for possible use as middleware in robot system integration. There is a need for bulky binary data transmission between distributed robot S/W components. Since the UPnP utilizes SOAP protocol for message transmission, however, it is not efficient to send bulky binary data. In order to overcome this weak point, this paper proposes UPnP-MTOM, MTOM (Message Transmission Optimization Mechanism) implementation over UPnP, as an efficient way for bulky binary data transmission with UPnP messages. This paper presents our implementation method and experimental results of the UPnP-MTOM implementation.

• Wind and Structures
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• v.5 no.2_3_4
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• pp.127-140
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• 2002

This paper presents some of the results of a project whose aim has been to produce a full simulation model which would determine the efficacy of pesticides for use by both farmers and the bio-chemical industry. The work presented here describes how crop architecture can be mathematically modelled and how the mechanics of pesticide droplet capture can be simulated so that if a wind assisted droplet-trajectory model is assumed then droplet deposition patterns on crop surfaces can be predicted. This achievement, when combined with biological response models, will then enable the efficacy of pesticide use to be predicted.

• Proceedings of the Korean Information Science Society Conference
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• 2007.06d
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• pp.537-540
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• 2007

분산된 서비스의 통합의 중요성이 커지고 있는 최근의 유비쿼터스 환경에서 SOA(Service Oriented Architecture)의 구현기술인 웹 서비스는 이러한 분산된 서비스를 연계하는 표준기술로서 기업내, 외부뿐만 아니라 방송/통신 융합, 정보가전/홈네트워크, 임베디드 환경 등 다양한 분야에서 사용되어 지고 있다. 본 논문에서는 홈네트워크에서 사용되는 디바이스등을 상호 이질적인 플랫폼이나 프로토콜에 유연하게 제공하기 위한 서비스 변환 게이트웨이 역할을 하는 SCG 엔진(Service Convergence Gateway Engine)과 서비스 연계의 표준기술로 자리잡고 있는 웹 서비스를 기반으로 SOA를 지원하고 S/W Service와 Application Component간의 연동을 위한 경량화된 Backbone의 역할을 수행하는 ESB(Enterprise Service Bus)를 사용하여 서비스를 통합하고 관리하는 구조를 제안 한다.

• Proceedings of the KIEE Conference
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• 1987.07b
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• pp.1449-1453
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• 1987

A microprogrammable Bit Slice Sinal Processor for image processing is implemented. Processing speed is increased by the parallelism in horizontal microprogram using 120bits microcode, pipelined architecture, 2 bank memory switching that interfaces with the Host through DMA, a variable clock control, overflow checking H/W,look-up table method and cache memory. With this processor, a DCT algorithm which uses 2-D FFT is performed. The execution time for $512{\times}512{\times}8$ image is 12 sec when 16 bit operation is runned, and the recovered image has acceptable quality with MSE 0.276%.

• Proceedings of the KIEE Conference
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• 2004.07e
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• pp.120-122
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• 2004

This paper describes the digital relay simulator by use of DSP for digital relay test. The simulator software has EMTP simulation data file conversion. user define simulation data generation. data analysis engine. etc. The simulator hardware design uses 32bit floating point DSP architecture to achivev flexibility and high speed operation.

• Proceedings of the KOSOMBE Conference
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• v.1997 no.11
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• pp.537-540
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• 1997

The quantitative comparison of brain architecture across different subjects requires a common coordinate system, with respect to which the spatial variability of features form different individuals can be expressed. We have developed and implemented an image warping technique which is based on an elastic body deformation. The resulting 2D deformation map can be used to quantify anatomic differences between subjects. The technique's accuracy is tested, by warping 2D magnetic resonance images of age seventies into Talairach atlas.

• Transactions of the Korean Society for Noise and Vibration Engineering
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• v.24 no.12
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• pp.948-953
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• 2014

Many studies using the assumed mode method have been found for the free vibration analysis of stiffened plate with known elastic boundary conditions. However many local structures such as tank edges and equipment foundations consist of connected structures and it is very difficult to find suitable elastic boundary conditions. In this study combined polynomials which satisfy simply and fixedly supported boundary conditions are proposed. The proposed method has been applied to tanks which bounded by bulkhead and a deck. The results of this study shows good agreements with these obtain by the FEA S/W(Patran/Nastran).

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2012.07a
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• pp.115-116
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• 2012

최근 차세대 영상 기술로 홀로그래피가 많은 주목을 받고 있다. 컴퓨터를 이용한 홀로그램 생성 방법(computer generated hologram, CGH)을 많이 사용하고 있는데 CGH는 많은 연산량이 요구되기 때문에 실시간의 CGH를 위해서 FPGA나 GPU를 이용한 연산 방법이 주로 사용되고 있다. 하드웨어를 기반으로 하여 구현할 경우에 내부 시스템의 비트 제한으로 인하여 S/W와 같은 품질을 얻을 수 없다. 따라서 본 논문에서는 품질의 저하를 최소화하면서 하드웨어의 자원을 최대한 감소시킬 수 있는 하드웨어 비트 너비를 분석하여 가이드라인을 제시하고자 한다.

• Proceedings of the Korean Information Science Society Conference
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• 2005.11b
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• pp.451-453
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• 2005

최근 대규모의 분산 시스템을 통합, 구축하기 위한 S/W설계 방법론으로 웹 서비스를 구현 기술로 한 서비스-지향 구조(Service-Oriented Architecture) 개념이 등장하였다. SOA를 기반으로 조립되는 서비스간에 상호 작용하는 데이터는 인터페이스를 통한 형식적인 검증뿐 아니라 사용자의 의도에 맞게 사용될 수 있는지에 대한 실질적인 검증도 필요하다. 본 논문은 서비스-지향 구조에서 서비스간에 상호 작용하는 데이터의 오류를 실시간으로 탐지하고 데이터의 제약 조건을 학습시킴으로써 개발자의 수고를 덜고 e-business 시스템과 같이 상호 작용이 많은 시스템의 데이터를 효과적으로 관리할 수 있는 서비스를 개발한다.

• ETRI Journal
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• v.32 no.1
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• pp.1-10
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• 2010

In this paper, we present a fast Fourier transform (FFT) processor with four parallel data paths for multiband orthogonal frequency-division multiplexing ultra-wideband systems. The proposed 128-point FFT processor employs both a modified radix-$2^4$ algorithm and a radix-$2^3$ algorithm to significantly reduce the numbers of complex constant multipliers and complex booth multipliers. It also employs substructure-sharing multiplication units instead of constant multipliers to efficiently conduct multiplication operations with only addition and shift operations. The proposed FFT processor is implemented and tested using 0.18 ${\mu}m$ CMOS technology with a supply voltage of 1.8 V. The hardware- efficient 128-point FFT processor with four data streams can support a data processing rate of up to 1 Gsample/s while consuming 112 mW. The implementation results show that the proposed 128-point mixed-radix FFT architecture significantly reduces the hardware cost and power consumption in comparison to existing 128-point FFT architectures.