• 한국재료학회지
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• 제18권9호
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• pp.507-510
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• 2008

Electrical properties of multi-channel metal-induced unilaterally precrystallized polycrystalline silicon thin-film transistor (MIUP poly-Si TFT) devices and circuits were investigated. Although their structure was integrated into small area, reducing annealing process time for fuller crystallization than that of conventional crystal filtered MIUP poly-Si TFTs, the multi-channel MIUP poly-Si TFTs showed the effect of crystal filtering. The multi-channel MIUP poly-Si TFTs showed a higher carrier mobility of more than 1.5 times that of the conventional MIUP poly-Si TFTs. Moreover, PMOS inverters consisting of the multi-channel MIUP poly-Si TFTs showed high dynamic performance compared with inverters consisting of the conventional MIUP poly-Si TFTs.

• 한국정보과학회:학술대회논문집
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• 한국정보과학회 2008년도 한국컴퓨터종합학술대회논문집 Vol.35 No.1 (B)
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• pp.292-297
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• 2008

본 논문은 FPGA 기반 설계에서 주변보다 급격한 온도 변화를 보이는 hotspot들을 탐지하기 위한 열 감지 센서 수를 정하고, 센서의 놓여야 할 배치 장소를 결정하는 알고리즘을 제안한다. 열 감지 센서로는 동적으로 설계가 가능한 ring oscillator 센서 기술을 사용한다는 가정 하에, 센서의 사용 개수를 최소화함과 동시에 최적의 센서 배치 위치 찾는다. 기존의 연구의 단점은 센서가 감지하는 영역 범위를 적당한 크기의 정사각형으로 간주하였기에, 실제 원형의 관측 범위를 보이는 센서 감지 영역의 현실을 올바로 반영하지 못하였으며, 또한 잘 알려진 회로 분할(partition) 기법에 의존한 휴리스틱으로 최적의 결과를 보장하지는 못하였다. 이와는 달리 본 연구에서는 센서의 관측 범위를 원형으로 할 수도 있게 함과 동시에 최적의 해를 보장하는 센서 할당 및 배치 알고리즘을 제안한다. 구체적으로 본 제안 알고즘에서는 소위 “Candidate Coloring 기법”을 통해 센서가 놓여야 할 모든 후보 영역을 표시하며, “Candidate Filtering 기법”을 통해 불필요한 후보 영역들을 완전히 삭제하여 탐색 공간을 줄이게 되며 (해의 최적 해는 항상 유지 되도록 하면서), 마지막으로 Branch-and-Bound 알고리즘을 적용해 최적의 센서 할당 및 배치 결과를 찾아내었다.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1998년도 하계종합학술대회논문집
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• pp.530-533
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• 1998

In this paper, a new scheme of a boosted voltage generator (BVG) is designed for low powr DRAM's. The designed BVG can supply stable $V_{pp}$ using a new circuit operting method. This method controls charge pumping capability by switching the supply voltage and ring oscillator frequency of driving circuit, so the BVG can save area and reduce the powr dissipation during $V_{pp}$ maintaining period. The charge pumping circuit of the BVG suffers no $V_{T}$ loss and is to be applicable to low-voltage DRAM's. $V_{pp}$ level detecting circuit can detect constant value of $V_{pp}$ against temperature variation. The level of $V_{pp}$ varies -0.55%~0.098% during its maintaining period. Charge pumping circuit can make $V_{pp}$ level up to 2.95V with $V_{cc}$ =1.5V. The degecting level of $V_{pp}$ level detecting circuit changes -0.34% ~ 0.01% as temperature varies from -20 to 80.deg. C. The powr dissipation during V.$_{pp}$ maintaining period is 4.1mW.W.1mW.

• JSTS:Journal of Semiconductor Technology and Science
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• 제15권4호
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• pp.462-470
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• 2015

In this study, we analyze the impacts of the trapezoidal fin shape of a double-gate FinFET on the electrical characteristics of circuits. The trapezoidal nature of a fin body is generated by varying the angle of the sidewall of the FinFET. A technology computer-aided-design (TCAD) simulation shows that the on-state current increases, and the capacitance becomes larger, as the bottom fin width increases. Several circuit performance metrics for both digital and analog circuits, such as the fan-out 4 (FO4) delay, ring oscillator (RO) frequency, and cut-off frequency, are evaluated with mixed-mode simulations using the 3D TCAD tool. The trapezoidal nature of the FinFET results in different effects on the driving current and gate capacitance. As a result, the propagation delay of an inverter decreases as the angle increases because of the higher on-current, and the FO4 speed and RO frequency increase as the angle increases but decrease for wider angles because of the higher impact on the capacitance rather than the driving strength. Finally, the simulation reveals that the trapezoidal angle range from $10^{\circ}$ to $20^{\circ}$ is a good tradeoff between larger on-current and higher capacitance for an optimum trapezoidal FinFET shape.

• JSTS:Journal of Semiconductor Technology and Science
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• 제13권6호
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• pp.622-634
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• 2013

The circuit level implementation of nanoscale Insulated Shallow Extension Silicon On Nothing (ISE-SON) MOSFET has been investigated and compared with the other conventional devices i.e. Insulated Shallow Extension (ISE) and Silicon On Nothing (SON) using the ATLAS 3D device simulator. It can be observed that ISE-SON based inverter shows better performance in terms of Voltage Transfer Characteristics, noise margin, switching current, inverter gain and propagation delay. The reliability issues of the various devices in terms of supply voltage, temperature and channel length variation has also been studied in the present work. Logic circuits (such as NAND and NOR gate) and ring oscillator are also implemented using different architectures to illustrate the capabilities of ISE-SON architecture for high speed logic circuits as compared to other devices. Results also illustrates that ISE-SON is much more temperature resistant than SON and ISE MOSFET. Hence, ISE-SON enables more aggressive device scaling for low-voltage applications.

• 전기전자학회논문지
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• 제24권2호
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• pp.446-452
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• 2020

본 논문에서는 실외용 움직임 감지에 적합한 K대역 마이크로파 움직임 감지 센서를 활용한 에너지 절감형 LED 모듈을 제안하였다. 헤어핀 형태의 마이크로스트립 공진기를 이용한 발진기를 설계하여 안정성을 높이고 제작이 쉽도록 하였다. 신호의 방사를 위해 송수신 2채널 패치 배열 안테나를 개발하여 적용하였다. 수신된 신호로부터 도플러 천이 값을 획득하기 위해 윌킨슨 전력분배기 및 링 하이브리드 혼합기를 개발하여 적용하였다. 신호의 안정성 및 원치 않는 외부잡음으로부터 보호하기 위해 쉴드 캔을 제작하여 장착하였다. 제안된 움직임 감지 센서를 실증용 LED 모듈에 장착하여 에너지 절감 성능을 모의실험을 통하여 검증하였다.

• 전자공학회논문지A
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• 제28A권10호
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• pp.821-829
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• 1991

In this paper, a BICMOS technology that has CMOS devices for digital application and bipolar devices for high voltage (80V) analog applications is presented. Basic concept to design BICMOS device is simple process technology without making too many performance trade-offs. The base line process is poly gate p-well CMOS process and three additional masking steps are added to improve bipolar characteristics. The key ingredients of bipolar integration are n+ buried layer process, up/down isolation process and p-well base process. The bipolar base region is formed simultaneously with the region of CMOS p-well area to reduce mask and heat cycle steps. As a result, hFE value of NPN bipolar transistor is 100-150(Ic=1mA). Collector resistance value is 138 ohm in case of bent type collector structure. Breakdown voltage of BVebo, BVcbo and BVceo are 21V, 115V and78V respectively. Threshold voltage is ${\pm}$1.0V for NMOS and PMOS transistor. Breakdown voltage of NMOS and PMOS transistor is obtained 22V and 19V respectively. 41 stage CMOS ring oscillator has 0.8ns delay time.

• 한국인터넷방송통신학회논문지
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• 제17권5호
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• pp.193-197
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• 2017

본 논문에서는 델타 시그마를 이용하여 고분해능의 주파수 튜닝 범위를 가지는 저전력 디지털 주파수 합성기를 제안한다. 의료 기기용 센서 장치는 배터리 사용 시간의 제약으로 인해 저전력, 고성능 RF (Radio Frequency) 트랜시버를 필요로 한다. 반도체 공정의 미세화로 인한 디지털 회로 설계 기법의 발전으로, 이전의 아날로그 회로 설계의 한계를 극복하고, 고성능의 집적화가 가능해 지고 있다. 따라서, 전력 소모를 줄이기 위해 디지털 회로 기반의 주파수 합성기를 설계했다. 높은 주파수 분해능을 가지기 위해 델타 시그마 변조기를 링 발진기에 적용하여, 소수부 튜닝을 구현했다. 모의실험을 통해 제안된 구조가 전력 및 분해능에서 우수한 성능을 보임을 확인하였다.

• 전자공학회논문지A
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• 제33A권11호
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• pp.1-9
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• 1996

In the following paper, new architectural algorithm of clock and data recovery circuit is proposed for 622.08 Mbps optical communication receiver. New algorithm makes use of charge pump PLL using voltage controlled ring oscillator and extracts 8-channel 77.76 MHz clock signals, which are delayed by i/8 (i=1,2, ...8), to convert and recover 8-channel parallel data from 662.08 Mbps MRZ serial data. This circuit includes clock genration block to produce clock signals continuously even if input data doesn't exist. And synchronization of data and clock is doen by the method which compares 1/2 bit delayed onput data and decided dta by extracted clock signals. Thus, we can stabilize frequency and phase of clock signal even if input data is distorted or doesn't exist and simplify receiver architecture compared to traditional receiver's. Also it is possible ot realize clock extraction, data decision and conversion simulataneously. Verification of this algorithm is executed by DESIGN CENTER (version 6.1) using test models which are modelized by analog behavior modeling and digital circuit model, modified to process input frequency sufficiently, in SPICE.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2002년도 합동 추계학술대회 논문집 정보 및 제어부문
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• pp.593-596
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• 2002

A design of clock and data recovery (CDR) circuit for the SONET OC-48 using a standard 0.18 ${\mu}m$ CMOS process has been performed. The phase detector and the charge pump must be able to operate at the 2.5 Gb/s input data speed and also accurately compare phase errors to reduce clock jitter. As a phase detector, the Hogge phase detector is selected but two transistors are added to improve the performance of the D-F/F. The charge pump was also designed to be placed indirectly input and output. A general ring oscillator topology is presented and simulated. It provides five-phase outputs and 220 MHz to 3.12 GHz tuning range.