• The Journal of the Korea institute of electronic communication sciences
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• v.16 no.3
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• pp.451-456
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• 2021

In order to improve the cell capacitance and scale down in capacitors of semiconductor memory devices, a stacked ONO structure has been introduced as a dielectric layer and thinning of these layers has been attempted continuously. However, many problems have emerged in the manufacturing process. In this study, L/L LPCVD system was used to suppress the growth of natural oxide film of about 10 Å, which was able to secure the capacitance of 3fF / cell. In addition, we investigated the effect of thinning of the dielectric film on the abnormal oxidation of the nitride film, and proposed a stable process control method for forming the dielectric film to ensure oxidation resistance.

• Journal of Sensor Science and Technology
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• v.4 no.4
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• pp.29-40
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• 1995

In this paper, the noise equivalent cicuits that is necessary to the formulation of D.C. and noise characteristics, residual component and input capacitance so as to analyze on the noise factors of the SIT is proposed. The simplest noise equivalent circuit is the model representing the mechanism of the SIT and the measured values in this model were found as small as the values of the shot-noise. In the source resistance inserted equivalent circuit is conformed that the shot-noise will be reduced by the negative-feedback effect of the source resistance. In oder to analyze the correct noise reduction factor, I proposed the equivalent circuit which the formulas of the source and drain resistance was induced. In the experiment which affirm the equivalent circuits, the influence of the signal source resistance and output load resistance on the residual component is small and the residual component can be expressed by the equivalent input noise resistance. Moreover, the input capacitance is 13.6 pF when the load resistance is $0{\Omega}$ and the capacitance which does not concern with the SIT operation directly, that is, gate wire etc, is 10pF or so.

• Journal of the Korean Ceramic Society
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• v.45 no.8
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• pp.493-496
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• 2008

Composite electrodes consisting of $CoMnO_2$ and carbon nanofibers(vapor grown carbon nanofiber, VGCF) with high electrical conducivity($CoMnO_2$/VGCF) were prepared on a porous nickel foam substrate as a current collector and their supercapacitive properties were investigated using cyclic voltammetry in 1 M KOH aqueous solution. The $CoMnO_2$/VGCF electrode exhibited high specific capacitance value of 630 F/g at 5 mV/s and excellent capacitance retention of 95% after $10^4$ cycles, indicating that the used VGCF played the important roles in reducing the interfacial resistance in the composite electrode to improve supercapacitive performance.

• The Transactions of the Korean Institute of Power Electronics
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• v.18 no.2
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• pp.145-152
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• 2013

Electrolytic capacitors used for smoothing DC link voltage is one of the major root causes of fault in power electronic system. The aging of aluminum electrolytic capacitors is expressed by the increase of their equivalent series resistance (ESR) and the reduction of their capacitance. Thus, the proposed technique in this paper is to measure capacitance, by comparing energy loss of DC link capacitors with stator resistor in electric machine. Condition of DC link capacitors can be estimated from the capacitance decrease rate between initial and aged capacitors. The results show that the proposed technique provides an easy, widely applicable and simple low cost solution for detecting dc link capacitor degradation.

• The Transactions of the Korean Institute of Electrical Engineers P
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• v.54 no.4
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• pp.163-170
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• 2005

This paper deals with an improved fault location algorithm with compensation ground capacitance through distributed parameter for a long parallel T/L. For the purpose of fault locating algorithm non-influenced by source impedance and fault resistance, the loop method was used in the system modeling analysis. This algorithm uses a positive and negative sequence of the fault current for high accuracy of fault locating calculation. Power system model of 160km and 300km long parallel T/L was simulated using EMTP software. To evaluate of the proposed algorithm, we used the several different cases 64 sampled data per cycle. The test results show that the proposed algorithm was minimized the error factor and speed of fault location estimation.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2000.05b
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• pp.216-221
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• 2000

This paper describes the analysis results on the PT ferroresonance at 154 kV GIS (gas Insulated substation by EMTP(Electro- magnetic Transient Program). We had simulated the PT ferroresonance between a potential transformer(PT) and an open circuit breaker's grading capacitance. The ferroresonance leads to very large power frequency overvoltages on PT bus and subsequent insulation failure. The large power can be supplied to the PT by the high voltage on the opened circuit due to the grading capacitance and equivalent capacitance of the buses during the ferroresonance. The damping circuit connected on the secondary winding were considered in the model. The actual countermeasure include a saturable inductor and a resistor series-mounted, but the 2 ohms of damping resistance was used in the computationl model.

• Proceedings of the KIEE Conference
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• 1999.07e
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• pp.2076-2079
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• 1999

This paper describes the analysis results on the PT ferroresonance at 154 kV GIS (gas Insulated substation by EMTP (Electro-magnetic Transient Program). We had simulated the PT ferroresonance between a potential transformer(PT) and an open circuit breaker's grading capacitance. The ferroresonance leads to very large power frequency overvoltages on PT bus and subsequent insulation failure. The large power can be supplied to the PT by the high voltage on the opened circuit due to the grading capacitance and equivalent capacitance of the buses during the ferroresonance. The damping circuit connected on the secondary winding were considered in the model. The actual countermeasure include a saturable inductor and a resistor series-mounted, but the 2 ohms of damping resistance was used in the computational model.

• Magazine of the Korean Society of Agricultural Engineers
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• v.40 no.6
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• pp.79-88
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• 1998

This study was conducted to measure the moisture content of soil using RF impedance in the range of 1 to 30MHz. Considering the water potential flow in the soils, two types of sensor such as parallel cylinder and perpendicular plate type were fabricated and tested. The capacitance and resistance of sonsors for soil samples having moisture content range of 2 to 27% were measured by Q-meter (HP4342). The higher soil moisture content was and the larger soil bulk density was, the more the capacitance of sensors increased. To eliminate the effect of bulk density on measuring soil moisture content using RF impedance, two kinds of model having the density independent functions such as the ratio of capacitance change to conductance change and weight of water and dry soils respectively were developed and estimated by regression analysis.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1999.11a
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• pp.173-176
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• 1999

Continuing improvement of microprocessor performance involves in the devece size. This allow greater device speed, an increase in device packing density, and an increase in the number of functions that can reside on a single chip. However this has led to propagation delay, crosstalk noise, and power dissipation due to resistance-capacitance(RC) coupling become significant due to increased wiring capacitance, especially interline capacitance between the metal lines on the same metal level. Becase of pattering MSSQ (Methylsilsequioxane), we use RIE(Reactive ton Etching) which is a good anisotrgpy. In this study, according as we control a flow rate of CF$_4$/O$_2$ gas, RF power, we analysis by using ${\alpha}$ -step, SEM and AFM,

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.11
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• pp.25-31
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• 2016

Parasitic capacitance and resistance of FinFET transistors are the important components that determine the frequency performance of the circuit. Therefore, the researchers in our group developed more accurate parasitic capacitance and resistance for FinFETs than BSIM-CMG. To verify the RF performance, proposed model was applied to design an LNA that has $S_{21}$ more than 10dB and center frequency more than 60GHz using HSPICE. To verify the accuracy of the proposed model, mixed-mode capability of 3D TCAD simulator Sentaurus was used. $S_{21}$ of LNA was chosen as a reference to estimate the error. $S_{21}$ of proposed model showed 87.5% accuracy compared to that of Sentaurus in 10GHz~100GHz frequency range. The $S_{21}$ accuracy of BSIM-CMG model was 56.5%, so by using the proposed model, the accuracy of the circuit simulator improved by 31%. This results validates the accuracy of the proposed model in RF domain and show that the accuracies of the parasitic capacitance and resistance are critical in accurately predicting the LNA performance.