• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 1999년도 춘계학술대회 논문집
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• pp.26-29
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• 1999

The I-V characteristics of the n-channel offset gated poly-Si TETs have been systematically investigated in order to analyse the effects of offset region. The on currents are reduced due to the series resistance by the offset length and there is no kink phenomenon in offset devices. The off currents of the offset gated TFTs are remarkably reduced to 10$^{-12}$ A independent of gate and drain voltage because the electric field is weakened by the increase of the depletion region width near the drain region. It is shown that the offset regions behave as a series resistance and reduce lateral and vertical electric field.

• 대한조선학회논문집
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• 제59권4호
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• pp.243-250
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• 2022

In the design stage of hull forms, a fast prediction method of resistance performance is needed. In these days, large test matrix of candidate hull forms is tested using Computational Fluid Dynamics (CFD) in order to choose the best hull form before the model test. This process requires large computing times and resources. If there is a fast and reliable prediction method for hull form performance, it can be used as the first filter before applying CFD. In this paper, we suggest the offset-based performance prediction method. The hull form geometry information is applied in the form of 2D offset (non-dimensionalized by breadth and draft), and it is studied using Convolutional Neural Network (CNN) and adapted to the model test results (Residual Resistance Coefficient; C_R). Some additional variables which are not included in the offset data such as main dimensions are merged with the offset data in the process. The present model shows better performance comparing with the simple regression models.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 1999년도 추계학술대회 논문집
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• pp.457-460
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• 1999

The effects of electrical positive stress on n-channel LDD and offset structured poly-Si TFT\`s have been systematically investigated in order to analyze the transfer curve\`s shift mechanism. It has been found that the LDD and offset regions behave as a series resistance that reduce the electric field near drain. Hot carrier effects are reduced because of these results. After electrical stress transfer curve’s shift and variation of the off-current are dependent upon the offset length rather than offset region’s doping concentration. Variation of the subthreshold slope is dependent upon offset region’s doping concentration as well as offset length.

• 한국태양에너지학회 논문집
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• 제33권6호
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• pp.92-97
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• 2013

This paper proposes DC offset current compensation method of transformerless fuel cell/PV PCS. DC offset current is generated by the unbalanced internal resistance of the switching devices in full bridge topology. The other cause is the sensitivity of the current sensor, which is lower than DSP in resolution. If power converter system has these causes, the AC output current in the inverter will generate the DC offset. In case of transformerless grid-connected inverter system, DC offset current is fatal to grid-side, which results in saturating grid side transformer. Several simulation results show the difficulties of detecting DC offset current. Detecting DC offset current method consists of the differential amplifiers and PWM is compensated by the output of the Op amp circuit with integrator controller. PSIM simulation verifies that the proposed method is simpler and more effective than using low resolution current sensor alone.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2000년도 추계종합학술대회 논문집(2)
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• pp.160-163
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• 2000

In this paper, we propose an efficient technique to minimize the input offset of a dynamic latch comparator. We analyzed offset due to charge injection mismatching and unwanted positive feedback during sampling phase. The last one was only considered in the previous works. Based on the analysis, we proposed a modified dynamic latch with initialization switch. The proposed circuit was simulated using 0.65$\mu\textrm{m}$ CMOS process parameter with 5v supply. The simulation results showed that the input offset is less than 5mv at 200㎒ sampling frequency and the input offset is improved about 80% compared with previous work in 5k$\Omega$ input resistance.

• 한국전자파학회:학술대회논문집
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• 한국전자파학회 2001년도 종합학술발표회 논문집 Vol.11 No.1
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• pp.218-221
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• 2001

In this paper, High Q Inductor using negative resistance circuit and the ceramic inductor was designed and fabricated at 2GHz. It was Improved the inductor of Q=90 using a inductor with Q=30 added to negative resistance circuit at 2GHz. As a result, at the bias condition of 3V and 16mA, the output power and phase noise in the operation frequency 2.01GHz are 5dBm and -115.34dBc/Hz at 100kHz offset from carrier, respectively. Phase noise was improved -10dBc/Hz at 100kHz offset compared to only using ceremic inductor.

• 한국해양공학회지
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• 제8권2호
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• pp.157-165
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• 1994

Effect of an accelerated iso-thermal aging (375 degree C x 66days, 375 degree C x 200days) on elastic-plastic fracture resistance curve were examined in SA533B low alloy steel. Fracture toughness test are conducted by unloading compliance method at room temperature. But the apparent negative crack growth phenomenon, usually arise in partial unloading compliance test. The phenomenon of negative crack growth may be eliminated by the offset technique. There is no effect of aging on J sub(IC) and dJ/da in iso-thermal aged (375 degree C x 66 days) specimen, but there is very little effect in iso-thermal aged (375 degree C x 200 days) specimen.

• 대한전자공학회논문지SD
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• 제43권10호
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• pp.97-103
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• 2006

본 논문에서는 무선 수신기용 down-conversion mixer에서 발생하는 2차 비선형과 DC-offset 문제를 향상시키는 방법을 제시하였다. 제안 된 회로에서는 간단한 수식적인 분석으로부터 2차 혼변조 왜곡 성분과 DC-offset 성분은 duty cycle 조절을 통하여 제거 될 수 있음을 알 수 있었다. 제안 된 방법을 가지고 $0.13{\mu}m$ RF CMOS 공정을 사용하여 출력 저항에 5%의 오차를 어 모의실험을 수행하여 보았다. 실험 결과 출력 저항에 5%의 오차를 주었을 때, IIP2(second-order input intercept point)와 DC-offset은 각각 2.04dBm와 22mV의 값을 가졌으나, 여기에서 제안된 방법을 통하여 IIP2는 38.8dBm로, DC-offset은 $777{\mu}V$로 각각 향상됨을 확인 할 수 있었다.

• 전자공학회논문지A
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• 제33A권3호
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• pp.96-106
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• 1996

One of the major problems for poly-Si TFTs is the large off state leakage current. LDD (lightly doped drain) and offset gated structures have been employed in order to reduce the leakage current. However, these structures also redcue the oN current significantly due to the extra series resistance caussed by the LDD or offset region. It is desirable to have a device which would have the properties of the offset gated structure in the OFF state, while behaving like a fully gated device in the oN state. Therefore, we propose a new thin film transistor with pnp junction gate which reduce the leakage curretn during the OFF state without sacrificing the ON current during the ON state.

• 설비공학논문집
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• 제13권4호
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• pp.271-287
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• 2001

This paper has been made to investigate the thermal performance characteristics for the several types of layered aluminum heat sinks with offset-strip fin. Heat sinks with different fin height, fin length, number of fin layer and slanted fin are prepared and tested for natural convection as well as forced convection. The experimental results for layered heat sink(LHS) are compared to those for advanced pin fin heat sink (PHS) so that the appropriate heat sink can be designed or chosen according to the heating conditions. The overall heat transfer performances for LHS are almost comparable to those of PHS under natural convection, and become 1.2∼1.5 times as high as those of PHS under forced convection situation. This study shows that fin height and number of fin layer re important parameters, which have a serious influence on thermal performance for layered heat sinks.