• 제목/요약/키워드: Reset period

검색결과 75건 처리시간 0.022초

AC PDP에서 고속 어드레싱을 위한 네거티브 리셋 파형 및 구동회로의 구현 (Implementation of the Negative Reset Waveform and Driving Circuit for High Speed Addressing in AC PDP)

  • 임현묵;임승범;이준영;강정원;홍순찬
    • 전력전자학회:학술대회논문집
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    • 전력전자학회 2007년도 추계학술대회 논문집
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    • pp.215-217
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    • 2007
  • Recently, the demand for high definition TV is being increased by beginning of the digital broadcasting. The higher resolution of PDP is, the longer addressing time become, then, the sustain period for display image decreases. Because of the reason, dual-scan method which synchronously write information of an image on top and bottom of the screen is used for the high definition PDP. However, as the price competition of PDP becomes severe, we can`t avoid turning to a single-scan method which uses only a half of an expensive address IC. Accordingly, the sustain period becomes much shorter than prior method. In case of XGA level, it is impossible to display, eventually. In this paper, we are going to prove usefulness by realizing negative reset waveform and the driving circuit for high speed addressing.

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중간간격을 갖는 교류형 플라즈마 디스플레이 표시기의 소거파형 연구 (Design of Erase Waveform for Stabilizing Reset Discharge in Mid-gap AC Plasma Display Panels)

  • 윤수한;서정현
    • 전기학회논문지
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    • 제60권5호
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    • pp.993-998
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    • 2011
  • In this paper we suggest new criteria for the classification of the electrode gap between common and scan electrodes. The electrode gap is categorized as a short, middle, and long gap according to the criteria. Among these structures, we focus on the erase waveform of a mid-gap structure. we report an unstable discharge arising from the erase ramp period in a mid-gap structure. Based on the Vt close curve, we analyze the unstable discharge at various conditions. Our analysis reveals that the unstable discharge is ignited between surface electrodes and caused by un-erased wall charges accumulated on the outer edges of electrodes. By reducing the voltage level of the last sustain pulse, the problem is solved.

NTT/BT 프로토콜의 성능 분석 (Performance Analysis of NTT/BT Protocol)

  • 이창훈;백상엽;이동주
    • 한국경영과학회지
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    • 제22권2호
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    • pp.99-123
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    • 1997
  • Performance analysis of NTT/BT protocol is investigated, which is a GFC (Generic Flow Control) ptotocol in ATM (Asynchronous Transfer Mode ) network and is based on cyclic reset mechanism. THe mean cell delay time is proposed as a performance measure of NTT/BT protocol. The mean cell delay time is defined as the duration from the instant the cell arrives at the transmission buffer until the cell is fully transmitted. The process of cell transmission can be described as a single server queueing modle with two dependent services. By utilizing this model, mean cell delay time is obtained and sensitivity of the factors such as window size and reset period is also analysed.

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NC 선반가공에서 공구 조정주기의 경제적 설계 (Economic Design of Tool Resetting Period in NC Machining)

  • 배문택;윤원영;목학수
    • 한국정밀공학회지
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    • 제15권6호
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    • pp.33-39
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    • 1998
  • This paper is related to economic design of tool-resetting period in NC machining. In NC lathe machining, the mean and variance of components dimension fluctuate in slow time and we should reset tool program to compensate the variation from the fluctuation. In this paper. we propose the procedure determining the optimal resetting period based on the total expected operating cost which consists of resetting cost and the quality cost related to dimension variation. As a case study, using experimental data about dimension changes of a lathe machining, we obtain the regression equations of mean and variance of the dimension fluctuation, total expected operating cost, and optimal resetting period.

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Address and Display Period Complex Driving for Expanding Gray Scale

  • Jung, Kwang-Sig;Kim, Gop-Sig;Shin, Seung-Rok;Chae, Su-Yong;Kim, Dae-Hwan;Yoo, Min-Sun;Cho, Yoon-Hyoung
    • 한국정보디스플레이학회:학술대회논문집
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    • 한국정보디스플레이학회 2005년도 International Meeting on Information Displayvol.I
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    • pp.647-650
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    • 2005
  • A new driving scheme, Address and Display Period Complex Driving for Expanding Gray Scale(ACE), is proposed by mixing Address Display period Separated(ADS) and Address While Display(AWD). In this method scan lines are divided in blocks driving by AWD and scan lines in block progress sequential high speed addressing. ADS driving get accomplished in low gray level for expanding gray scale. Scan time is reduced and the number of subfields is increased by high speed addressing of ACE. That expands the gray scale and decreases the dynamic false contour. Also, that improves contrast by using ramp reset.

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AC PDP의 저온에서 어드레스 방전 지연 시간 개선에 관한 연구 (A Study on the Improvement of the Low Temperature Address Discharge Time Lag of High-Xe Content AC PDP)

  • 김지용;김선;이석현;이정해;김준엽
    • 대한전기학회:학술대회논문집
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    • 대한전기학회 2005년도 제36회 하계학술대회 논문집 C
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    • pp.2156-2159
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    • 2005
  • ADS(Address Display Period Separation) driving method has been considered to be the most appropriate driving technique for AC PDP. ADS driving method is composed of reset, address, sustain and erase period. Therefore, a long time should be allocated to an address period, which results in a reduction of brightness. To realize a high luminance and high picture quality, it is necessary to high speed addressing. However, address discharge time lag increases as the temperature decreases, which can cause the misfiring and low picture quality In this paper, the electric field effect and priming particle effect are investigated in order to reduce the address discharge time lag at low temperature. Address discharge time lag was reduced effectively when the priming particles are provided.

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AC PDP의 Image Sticking 현상에 관한 연구 (A Study on the Image Sticking Phenomenon in AC PDP)

  • 임성현;심경렬;김동현;이호준;박정후;김규섭
    • 대한전기학회:학술대회논문집
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    • 대한전기학회 2002년도 하계학술대회 논문집 C
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    • pp.1640-1643
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    • 2002
  • Image sticking, the phenomenon that the previously displayed pattern still remains after the image is changed into different image, is one of the most serious problem in realizing high picture quality. In this paper, we tried characterizing this undesirable feature in terms of the luminance and the intial firing voltage at ramp up time in reset period. It was found that the cell located at the boundary of previous image pattern show low firing voltage and high background luminance. And the results show that the degree of the image sticking is severely affected by discharge duration and the length of the sustain period.

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Design of Cost-Effective Driving Waveform Based on Vt Close Curve Analysis in AC Plasma Display Panel

  • Cho, Byung-Gwon;Tae, Heung-Sik;Ito, Kazuhiro;Song, Jun-Weon;Lee, Myoung-Kyu;Kim, Sang-Chul;Jung, Nam-Sung;Lee, Kwang-Sik
    • 한국정보디스플레이학회:학술대회논문집
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    • 한국정보디스플레이학회 2005년도 International Meeting on Information Displayvol.I
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    • pp.251-254
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    • 2005
  • A new driving waveform was proposed to reduce the cost in PDP-TV based on Vt close curve by eliminating the common (X) board under the conventional 42-inch panel structure. Due to the serious misfiring problem during a sustain-period when applying the new driving waveform, the wall voltage was measured and analyzed after the reset-period using Vt close curve. As a result of adopting the proposed driving waveform designed using Vt close curve analysis, the cost of PDP module could reduce compared with the conventional PDP module without any misfiring discharge.

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AC PDP의 Image sticking 현상에 대한 연구 (The study on the image sticking phenomenon in AC PDP)

  • 임성현;심경렬;김동현;이호준;박정후;김규섭
    • 한국전기전자재료학회:학술대회논문집
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    • 한국전기전자재료학회 2002년도 춘계합동학술대회 논문집
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    • pp.158-161
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    • 2002
  • Among the characteristics of image quality in AC PDP, the serious problem is the image sticking. It can be explained that the previous pattern still remains after the image is changed into different image. In this paper, in case that the length of sustain period and the continued time of still image is varied, the image sticking phenomenon is investigated as the Initial firing voltage at ramp up time during reset period.

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플라즈마 디스플레이 패널에서 부화면 시간동안 기입시간을 단축시키기 위한 수정된 구동파형 (Modified Driving Method for Reducing Address Time During Subfield Time in AC PDP)

  • 조병권
    • 전자공학회논문지
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    • 제52권1호
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    • pp.135-139
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    • 2015
  • 플라즈마 디스플레이 패널의 각 부화면 시간동안 기입 방전의 지연시간을 각각 조사하였고 오방전이 발생하지 않는 범위내에서 추가 주사전압의 높이를 다르게 인가하여 모든 부화면 시간동안 기입방전 지연시간을 단축시키기 위한 수정된 구동방법을 제시한다. AC PDP에서 첫번째 초기화 기간 동안 주사전극에 높은 상승 경사파 전압을 인가하여 약한 플라즈마 방전이 발생하고 셀 내부에서 프라이밍 입자와 벽전하 생성을 유도한다. 생성된 벽전하는 셀 내부 벽전압이 되므로 기입기간 중 기입전압과 더해져서 기입 방전을 일으킨다. 그러나 셀 내부의 벽전하는 시간이 지나면서 점차 소멸되므로 1 TV 프레임 시간 동안 각 부화면 시간동안 기입방전은 늦게 발생한다. 첫 번째 부화면 시간에는 초기화 기간 동안 상승 경사파를 갖는 높은 전압에 의해 벽전하가 많이 남아 있으므로 첫 번째 기입 방전은 다른 부화면 시간보다 빠르게 형성된다. 한편, 두 번째부터 마지막 부화면 시간까지의 기입 방전 생성시간은 셀 내의 벽전하 소멸에 의하여 점차적으로 늦어진다. 본 연구에서는 각 부화면 시간동안 기입방전의 시간지연을 조사하였고, 부화면 시간의 기입기간 마다 추가 주사전압을 다르게 인가하여 전체 기입방전지연시간을 단축시켰다.