• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.5
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• pp.625-631
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• 2014

We propose a compact power-on reset circuit consisting of a switched capacitor, a capacitor, and a Schmitt trigger inverter. A switched capacitor working with a clock signal charges the capacitor. Thus, the voltage across the capacitor is increased toward the supply voltage. The circuit provides a reset pulse until the voltage across the capacitor reaches the high threshold voltage of the Schmitt trigger inverter. The proposed circuit is simple, compact, has no static power consumption, and works for a wide range of power-on rising times. Furthermore, the clock signal is available while the reset pulse is activated. The proposed circuit works for up to 6 s of power-on rising time, and occupies a $60{\times}30{\mu}m^2$ active area.

• Journal of IKEEE
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• v.25 no.1
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• pp.206-211
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• 2021

This paper proposes a Self-Reset Zero-Current Switching (ZCS) Circuit for thermoelectric energy harvesting. The Self-Reset ZCS circuit minimizes the operating current consumed by the voltage comparator, thereby reduces the power consumption of the energy harvesting circuit and improves the energy conversion efficiency by adding the self-reset function to the comparator. The Self-Reset ZCS circuit shows 3.4% of improvement in energy efficiency compared to the energy harvesting system with the conventional analog comparator ZCS for the output/input voltage ratio of 5.5 as a result of circuit simulation. The proposed circuit is useful for improving the performance of the wearable and bio-health-related harvesting circuits, where low-power and energy-efficient thermoelectric energy harvesting is needed.

• ETRI Journal
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• v.30 no.5
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• pp.644-652
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• 2008

In this paper, a low-power CMOS interface circuit is designed and demonstrated for capacitive sensor applications, which is implemented using a standard 0.35-${\mu}m$ CMOS logic technology. To achieve low-power performance, the low-voltage capacitance-to-pulse-width converter based on a self-reset operation at a supply voltage of 1.5 V is designed and incorporated into a new interface circuit. Moreover, the external pulse signal for the reset operation is made unnecessary by the employment of the self-reset operation. At a low supply voltage of 1.5 V, the new circuit requires a total power consumption of 0.47 mW with ultra-low power dissipation of 157 ${\mu}W$ of the interface-circuit core. These results demonstrate that the new interface circuit with self-reset operation successfully reduces power consumption. In addition, a prototype wireless sensor-module with the proposed circuit is successfully implemented for practical applications. Consequently, the new CMOS interface circuit can be used for the sensor applications in ubiquitous sensor networks, where low-power performance is essential.

• JSTS:Journal of Semiconductor Technology and Science
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• v.3 no.2
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• pp.83-88
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• 2003

The reset operation of a CCD image sensor was improved using charge trapping of a MOS structure to realize a loe voltage driving. A DC bias generating circuit was added to the reset structure which sets reference voltage and holds the signal charge to be detected. The generated DC bias is added to the reset pulse to give an optimized voltage margin to the reset operation, and is controlled by adjustment of the threshold voltage of a MOS transistor in the circuit. By the pulse-type stress voltage applied to the gate, the electrons and holes were injected to the gate dielectrics, and the threshold voltage could be adjusted ranging from 0.2V to 5.5V, which is suitable for controlling the incomplete reset operation due to the process variation. The charges trapped in the silicon nitride lead to the positive and negative shift of the threshold voltage, and this phenomenon is explained by Poole-Frenkel conduction and Fowler-Nordheim conduction. A CCD image sensor with $492(H){\;}{\times}{\;}510(V)$ pixels adopting this structure showed complete reset operation with the driving voltage of 3.0V. The resolution chart taken with the image sensor shows no image flow to the illumination of 30 lux, even in the driving voltage of 3.0V.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.12 no.2
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• pp.282-289
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• 2008

To improve the efficiency of PDP TV, it should minimize the power losses transpired during AC-to-DC power conversion and PDP driving process. Generally the input power supply for PDP driving employes a two-stage power factor corrected converter, and it needs additional DC-to-DC converters to supply driving power for reset circuit ed sustain driver, which has high power consumption. However, such a circuit configuration has a difficulty for the PDP market requires low cost. To alleviate this problem, a new circuit composition is presented. It integrates input power supply with reset and sustain driver in a single power stack The input power supply of the proposed circuit has a single-stage structure to minimize power conversion loss, and it directly supplies power to the sustain driver so as to reduce the system size and cost.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2003.10a
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• pp.385-388
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• 2003

In this paper, a D-Latch is replaced by a memory cell on the proposed PFD to improve response tine by reducing reset me. The PFD has been simulated using HSPICE with a Hynix 0.35um CMOS process to prove the performance improvement.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.38 no.3
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• pp.31-39
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• 2001

In this paper, we proposed a new pixel circuit of the CMOS image sensor for high dynamic range operation, which is based on a multiple sampling scheme and a conditional reset circuit. To expand the pixel dynamic range, the output is multiple-sampled in the integration time. In each sampling, the pixel output is compared with a reference voltage, and the result of comparison may activate the conditional reset circuit. The times of conditional reset, N, during the integration will contribute to the increase of the dynamic range by the times of N. The test chip was fabricated with 0.65-${\mu}m$ CMOS technology (2-P, 2-M).

• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.4
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• pp.524-533
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• 2017

This paper presents a novel reset scheme for mm-scale sensing systems with stringent volume and area constraints. In such systems, multi-layer structure is required to maximize the silicon area per volume and minimize the system size. The multi-layer structure requires wirebonding connections for power delivery and communication among layers, but the area overhead for wirebonding pads can be significant. The proposed reset scheme exploits already existing power wires and thus does not require additional wires for system-wide reset operation. To implement the proposed reset scheme, a power management unit is designed to impose reset condition, and a reset detector is designed to interpret the reset condition indicated by the power wires. The reset detector uses a coupling capacitor for the initial power-up and a feedback path to hold the developed supply voltage. The prototype reset detector is fabricated in a $180-{\mu}m$ CMOS process, and the measurement results with the prototype mm-scale system confirmed robust reset operation over a wide range of temperatures and voltages.

• The Transactions of the Korean Institute of Power Electronics
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• v.10 no.6
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• pp.587-591
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• 2005

Driving Waveform of AC PDP in reset periode is increased and decreased with constant slope to improve dark room contrast ratio and image quality. But the slope and magnitude of ramp waveform are related to strong and weak discharge with temperature change in AC PDP. So this paper proposes a methods of changing the slope and magnitude of ramp waveform during reset periode according to temperature change in AC PDP. Experimental variable factors ire chosen to setup slope, setdown slope, and -Vy voltage magnitude in Y sustain electrode. The proposed methods are expected to compensate for effect of the temperature change, causing misfiring in high and low temprature, with varing the slope and magnitude of ramp voltage during reset period and improve image quality.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• v.9 no.2
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• pp.685-688
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• 2005

An efficient sustain driver and a useful reset circuit composition technique are proposed for plasma display panel drive. The proposed sustain driver uses a series resonance between an external inductor and a panel to recover the energy dissipated by a capacitive displacement current of PDP. It consists of four switching devices, an inductor, and external capacitors, which supply sustain voltage sources. Although the amplitude of an input voltage source is twice as high as that of conventional sustain drivers, average voltage stress imposed on power switching devices is nearly same in their values. Moreover, the input voltage source can be directly applied for the use of a reset voltage source. Owing to this scheme, the proposed sustain driver and the embedded reset circuit have a simple configuration. The operational principle and design example are given with theoretical analyses. The validity of the proposed drive system is verified through experiments using a prototype equipped with a 7.5-inch-diagonal AC plasma display panel.