• Journal of the Korean Society of Radiology
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• v.5 no.5
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• pp.295-302
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• 2011

To n the field of nuclear medicine, with regard to checking regular patients, from the moment they register up to the doctor's diagnosis, the person in charge of the checks can find errors in the diagnosis, reexamine, reanalyze the results or save images to PACS. Through this process, the results obtained from the readings are delayed due to checks and additional tests which occur in hospitals, causing patient satisfaction and affected reliability. Accordingly, the purpose is to include visual inspection of the results to minimize error, improve efficiency and increase patient satisfaction. Nuclear medicine and imaging tests from examines at Asan Medical Center, Seoul, from March 2008 to December 2008, were analyzed for errors. The first stage, from January 2009 to December 2009, established procedures and know-how. The second stage from January 2010 until June 2010 conducted Pre-and Post-filtering assessment, and the third stage from July 2010 until October 2010 consisted of cross-checks and attaching stickers and comparing error cases. Of 92 errors, the 1st, 2nd and 3rd stage had 32 cases, and there were 46 cases after the 4th stage, with the overall errors reduced by 74.3% from 94.6%. In the field of general nuclear medicine, where various kinds of checks are performed according to the patient's needs, analysis, image composition, differing images in PACS, etc, all have the potential for mistakes to be made. In order to decrease error rates, the image can continuously Cross-Check and Confirm diagnosis.

• The Journal of Korean Society for Radiation Therapy
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• v.26 no.2
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• pp.345-354
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• 2014

Purpose : We evaluated the usefulness of $Fraxion^{(R)}$ system and s-thermoplastic mask by analyzing setup error when stereotactic radiousurgery (SRS) was treated for brain metastasis. Materials and Methods : 6 patients who received definite diagnosis as brain metastasis between May 2014 and October 2014 were selected. 3 patients were immobilized s-thermoplastic mask and mouthpiece (group1), while $Fraxion^{(R)}$ system was used for the other 3 patients (group2). Cone Beam Computerized Tomography (CBCT) scan was acquired to register planning CT scan. The registration offset was compared for each group. We compared and reported the errors using maximum, minimum, mean, and standard deviation of registration offsets. Furthermore, We used the same method as patient specific quality assurance to verify absorbed dose of PTV. Results : The setup error which is registration offset was reduced 83% in x, 40% in y, and 92% in z-direction when $Fraxion^{(R)}$ system was used compared to the case of using s-thermoplastic mask and mouthpiece. In addition, using $Fraxion^{(R)}$ system showed improved results in rotational components, pitch (rotation along x-axis), roll (y), and yaw (z) which were reduced 64, 88, and 87% respectively compared to the case of using s-thermoplastic mask and mouthpiece. In dosimetry results, when s-thermoplastic mask and mouthpiece used, absorbed dose was reduce 83% compared to before and after registration. However, using $Fraxion^{(R)}$ system showed only 1.9%. All percentage were calculated with respect to average value. Conclusion : Using $Fraxion^{(R)}$ system including mouthpiece, Fraxion frame, frontpiece, and thermoplastic mask, showed better repeatability and precision compared to using s-thermoplastic mask and mouthpiece, which is consequently considered as more improved immobilization system.

• Radiation Oncology Journal
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• v.28 no.3
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• pp.166-176
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• 2010

Purpose: To determine the appropriate prostate planning target volume (PTV) margins for 3-dimensitional (3D) conformal radiotherapy (CRT) and intensity-modulated radiation therapy (IMRT) patients treated with an endorectal balloon (ERB) under our institutional treatment condition. Materials and Methods: Patients were treated in the supine position. An ERB was inserted into the rectum with 70 cc air prior to planning a CT scan and then each treatment fraction. Electronic portal images (EPIs) and digital reconstructed radiographs (DRR) of planning CT images were used to evaluate inter-fractional patient's setup and ERB errors. To register both image sets, we developed an in-house program written in visual $C^{++}$. A new method to determine prostate PTV margins with an ERB was developed by using the common method. Results: The mean value of patient setup errors was within 1 mm in all directions. The ERB inter-fractional errors in the superior-inferior (SI) and anterior-posterior (AP) directions were larger than in the left-right (LR) direction. The calculated 1D symmetric PTV margins were 3.0 mm, 8.2 mm, and 8.5 mm for 3D CRT and 4.1 mm, 7.9 mm, and 10.3 mm for IMRT in LR, SI, and AP, respectively according to the new method including ERB random errors. Conclusion: The ERB random error contributes to the deformation of the prostate, which affects the original treatment planning. Thus, a new PTV margin method includes dose blurring effects of ERB. The correction of ERB systematic error is a prerequisite since the new method only accounts for ERB random error.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.2C
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• pp.160-169
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• 2002

An ATM-PON (Passive Optical Network) system consists of an OLT (Optical Line Termination), multiple ONUs (Optical Network Units) and the optical fiber which has a PON (Passive Optical Network)configuration with a passive optical splitter. To avoid cell collisions on the upstream transmission, an elaborate procedure called as ranging is needed when a new ONU is installed. The ONU can send upstream cells according to the grant provided by the OLT after the procedure. To prevent collisions being generated by the variation of several factors, OLT must performs continuously the cell phase monitoring. It means that the OLT predicts the expected arrival time, monitors the actual arrival time for all upstream cells and calculates the error between the times. Accordingly, TC (Transmission Convergence) chip in the OLT needs a predictor which predicts the time that the cell will arrive for the current grant. In this paper, we implement the predictor by using shift registers of which the length is equivalent to the equalized round trip delay. As each register consists of 8 bit, OLT can identify which ONU sends what type of cell (ranging cell, user cell, idle cell, and mini-slot). Also, TC chip is designed to calculate the effective bandwidth for all ONUs by using the function of predictor. With the time simulation and the measurement of an implemented optical board, we verify the operation of the predictor.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.4
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• pp.833-838
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• 2011

RFID system in manufacturing industry is used to collect, categorize, and process the data of products. To install RFID system for a large factory, a large amount of wired data communication network is necessary for RS232 communication. If the installed location of RFID system in the factory is changed or extended, a reinstallment is required for the already installed wired data network. A large amount of time/financial reinvestment is necessary for such reinstallation. By using wireless data communication network, however, the initial installation and reinstallation are very simple. In this paper, we implemented a wireless communication system and RFID system. We used the CC1020 chip for wireless communication system and EM4095 chip for RFID system. CC1020 chip enables highly-reliable data communication, and by setting a simple status register, it can switch between transmitting/receiving status and it can choose the desired frequency of either 400 MHz or 900 MHz. Also, Communication range is 50 m, if external antenna is used. EM4095 is a chip for RFID reader system with the carrier frequency of 125 KHz. This chip can implement the reader system by connecting a small number of components. And EM4100 was used for RFID system. EM4100 is read-only type. Atmega128 is used to control a wireless communication system and RFID system. We confirm that the system can communicate without error up to 50 m from sender. In the paper, the circuit diagram and operation program for CC1020 and RFID system are presented. The system used in the experiment is shown in pictures, and the data movement pattern of CC1020 is shown in the diagram, and the performance of each transmission method is presented.

• Journal of Navigation and Port Research
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• v.43 no.6
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• pp.403-412
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• 2019

The characteristics of the manoeuvring motion of a ship are dependent on the ship type, as well as draft or speed in the same ship. In recent years, the number of extra-large vessels has increased significantly, which can cause enormous material and environmental damage in the event of a marine accident. Thus, the importance of ship maneuvering is increasing. The IMO has forced the officers to be trained in simulators through the STCW 95 amendment. However, FMSS is costly and difficult to access and the PC-based simulator has the disadvantage that only one person can engage in simulation. The purpose of this study was to solve the shortcomings of the FMSS and PC-based simulators by enabling multiple people to use their PCs to simulate based on a network. The simulator is implemented through the analysis and numerical calculation of the Nomoto model, Radar function mounting, data transfer protocol design, and GUI building. To verify the simulator, the simulation results were compared and analyzed with the test results of T.S. HANBADA according to the criteria of the Korean Register of Shipping(KR) and IMO standards for ship maneuverability. As a result, It showed a relative error of 0%~ 32.1% with an average of 13.7%, and it satisfied the IMO criteria for ship maneuverability.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.1A
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• pp.93-98
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• 2004

Serial ATA interface Is inexpensive comparatively and performance is superior. So it is suitable technology in demand that now require data transmission and throughput of high speed. This paper describes a design and implementation of Serial ATA Link layer about error detection and 8b/10b encoder/decoder for DC balance in frequency 150MHz. The 8b/10b Encoder is partitioned into a 5b/6b plus a 3b/4b coder. The logical model of the block is described by using Verilog HDL at register transistor level and the verified HDL is synthesized using standard cell libraries. And it is fabricated with $0.35{\mu}m$ Standard CMOS Cell library and the chip size is about $1500{\mu}m\;*\;1500{\mu}m$. The function of this chip has been verified and tested using testboard with FPGA equipment and IDEC ATS2 test equipment. It is used to frequency of 100MHz in verification processes and supply voltage 3.3V. The result of testing is well on the system clock 100MHz. The designed and verified each blocks may be used IP in the field of high speed serial data communication.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.9
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• pp.31-39
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• 2011

In this paper, we propose a signal readout system with small area and low power consumption for CNT sensor arrays. The proposed system consists of signal readout circuitry, a digital controller, and UART I/O. The key components of the signal readout circuitry are 64 transimpedance amplifiers (TIA) and SAR-ADC with 11-bit resolution. The TIA adopts an active input current mirror (AICM) for voltage biasing and current amplification of a sensor. The proposed architecture can reduce area and power without sampling rate degradation because the 64 TIAs share a variable gain amplifier (VGA) which needs large area and high power due to resistive feedback. In addition, the SAR-ADC is designed for low power with modified algorithm where the operation of the lower bits can be skipped according to an input voltage level. The operation of ADC is controlled by a digital controller based on UART protocol. The data of ADC can be monitored on a computer terminal. The signal readout circuitry was designed with 0.13${\mu}m$ CMOS technology. It occupies the area of 0.173 $mm^2$ and consumes 77.06${\mu}W$ at the conversion rate of 640 samples/s. According to measurement, the linearity error is under 5.3% in the input sensing current range of 10nA - 10${\mu}A$. The UART I/O and the digital controller were designed with 0.18${\mu}m$ CMOS technology and their area is 0.251 $mm^2$.

• Journal of Korean Society for Geospatial Information Science
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• v.22 no.3
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• pp.137-143
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• 2014

Recently, as new paradigm for government operation called government 3.0, government is actively operating policy opening and sharing public data. In addition, the Ministry of Land are operating an open platform integrated map service (the VWorld) which provides a variety of video contents such as the country's national spatial information, traffic information and three-dimensional building for the public. According to W3C Foundation's Open Data Status Report(2013), our country has the evaluated results that the part of the government's policy support and planning is good while the part of the data management is vulnerable. So our country needs the quality improvement for the data management. In addition, a digital aerial photograph image data is required to be up-to-date for the three-dimensional spatial object data. In this paper, we present the method for enhancement of the accuracy of vertical position and for maintainment of up-to-date vertical position. Our methods evaluate the data quality and analyze the cause of error of measurement utilizing the national standard quality assessment method. The result of research shows that the accuracy of vertical position is improved if the height of the building captain is adjusted by the quality assessment values and a three-dimensional model has up-to-date data if reconstruction and extension information of construction register is utilized.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.11
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• pp.14-23
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• 2002

Two implementation methods for SOVA (Soft Output Viterbi Algorithm)of Turbo decoder are applied and verfied. The first method is the combination of a trace back (TB) logic for the survivor state and a double trace back logic for the weight value in two-step SOVA. This architecure of two-setp SOVA decoder allows important savings in area and high-speed processing compared with that of one-step SOVA decoding using register exchange (RE) or trace-back (TB) method. Second method is adjusting the reliability value with a scaling factor between 0.25 and 0.33 in order to compensate for the distortion for a rate 1/3 and 8-state SOVA decoder with a 256-bit frame size. The proposed schemes contributed to higher SNR performance by 2dB at the BER 10E-4 than that of SOVA decoder without a scaling factor. In order to verify the suggested schemes, the SOVA decoder is testd using Xillinx XCV 1000E FPGA, which runs at 33.6MHz of the maximum speed with 845 latencies and it features 175K gates in the case of 256-bit frame size.