• Proceedings of the KIPE Conference
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• 전력전자학회 2000년도 전력전자학술대회 논문집
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• pp.752-755
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• 2000

This paper describes a new algorithm for active power filters which can be control source current symmetrically under unbalanced condition in power system. Positive sequency voltage is detected by symmetrical coordinate method and compensating reference current of active power filters is calculated using by accurate phase angle information of positive sequency voltage. The basic principle of the proposed method is described in detail and the conventional and proposed phase detecting methods are compared and discussed through the simulation results.

• Proceedings of the KIEE Conference
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• 대한전기학회 1988년도 추계학술대회 논문집 학회본부
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• pp.21-23
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• 1988

Microstepping drive of 3 phase VR step motor with 2 phase exciting scheme is proposed. Considering the presence of harmonic components of inductance, the current reference is calculated. The experimental results show high accuracy of divided step position and resonance or instability in operating range.

• Journal of the Korean Institute of Telematics and Electronics S
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• 제35S권5호
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• pp.11-16
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• 1998

DS/CDMA systems for the high speed communication require high code rats. In discrete time CDMA receivers, the performance degradation, caused by the phase difference between transmission code and reference code, increase the sampling frquency of the receiver. This increment of the sampling frequency makes hard to implement high speed CDMA systems. This paper analyzes the SIR(signal to interference Ratio) performance of the discrete time DS/CDMA system, based on the code phase difference. The results of this paper may be useful to study a low-sampling CDMA receiver.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 1989년도 한국자동제어학술회의논문집; Seoul, Korea; 27-28 Oct. 1989
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• pp.1028-1034
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• 1989

A method of analysis of the steady-state performance of induction motor with supply voltage controlled by cyclically-triggered inline thyristors is presented. Phase-variable model and asymmetrical components are not used in this analysis. Instead, Fast Fourier Transform technique and the method of multiple reference frames are employed to obtain the constant-speed performance of I.M. easily.

• Journal of the Institute of Electronics Engineers of Korea SC
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• 제46권2호
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• pp.72-77
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• 2009

In this paper, a 3.2Gb/s clock and data recovery (CDR) circuit for a high-speed serial data communication without the reference clock is described This CDR circuit consists of 5 parts as Phase and frequency detector(PD and FD), multi-phase Voltage Controlled-Oscillator(VCO), Charge-pumps (CP) and external Loop-Filter(KF). It is adapted the PD and FD, which incorporates a half-rate bang-bang type oversampling PD and a half-rate FD that can improve pull-in range. The VCO consists of four fully differential delay cells with rail-to-rail current bias scheme that can increase the tuning range and tuning linearity. Each delay cell has output buffers as a full-swing generator and a duty-cycle mismatch compensation. This materialized CDR can achieve wide pull-in range without an extra reference clock and it can be also reduced chip area and power consumption effectively because there is no additional Phase Locked- Loop(PLL) for generating reference clock. The CDR circuit was designed for fabrication using 0.18um 1P6M CMOS process and total chip area excepted LF is $1{\times}1mm^2$. The pk-pk jitter of recovered clock is 26ps at 3.2Gb/s input data rate and total power consumes 63mW from 1.8V supply voltage according to simulation results. According to test result, the pk-pk jitter of recovered clock is 55ps at the same input data-rate and the reliable range of input data-rate is about from 2.4Gb/s to 3.4Gb/s.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 2003년도 ICCAS
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• pp.1836-1840
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• 2003

This paper, we propose a new phase-locked loop (PLL) system with the controllable output phase, independent from the output frequency, and lock-up time. This PLL system has a dual control loop is described, the inner loop greatly improved VCO characteristic such as faster speed response as well as higher operation bandwidth, to minimize the effect of the VCO noise and the power supply variation and also get better linearity of VCO output. The main loop is the heart of this PLL which greatly improved the output frequency instability due to the external high frequency noise coupling to the input reference frequency also the main loop can control the output phase, independent from the output frequency, and reduce the lock-up time of the step frequency response. The experimental results confirm the validity of the proposed strategy.

• Proceedings of the KIEE Conference
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• 대한전기학회 1997년도 추계학술대회 논문집 학회본부
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• pp.456-458
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• 1997

The phase-lock technique is applied to a three-phase semi-bridge type battery charger system. Using an inner fast dynamic loop, the phase-locked voltage control (PLVC) technique of three-phase semi-bridge converter is proposed to give a frequency synchronism and to reduce the subharmonics due to the unbalance of transformer or power line. To protect the power devices, the two stage soft-start, function with softly locking the phase and softly increasing the current is presented. As limiting the reference voltage of the inner voltage control loop, muti-lock phenomena are removed on the PLVC loop. A current limit function is also proposed to limit the current of battery and converter. The proposed controller is confirmed through experiment results.

• ETRI Journal
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• 제35권2호
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• pp.218-225
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• 2013

The pull-out frequency of a second-order phase lock loop (PLL) is an important parameter that quantifies the loop's ability to stay frequency locked under abrupt changes in the reference input frequency. In most cases, this must be determined numerically or approximated using asymptotic techniques, both of which require special knowledge, skills, and tools. An approximating formula is derived analytically for computing the pull-out frequency for a second-order Type II PLL that employs a sinusoidal characteristic phase detector. The pull-out frequency of such PLLs can be easily approximated to satisfactory accuracy with this formula using a modern scientific calculator.

• Proceedings of the KIPE Conference
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• 전력전자학회 2007년도 하계학술대회 논문집
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• pp.428-430
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• 2007

Converter that is dc source equipment source's phase by reference control function that detect source's phase because should be done compulsorily use. Source's phase detect method there be method that use source's ac voltage directly by signal, and use methods that voltage detects status by PLL method and so on via point that '0' becomes usually. All above methods to detect phase are using, wrong action of phase detector converter's ailment or converter of burn can. Ths paper compares and examined usable phase detection method in source's frequency fluctuation presuming source's frequency using observer.

• Journal of the Optical Society of Korea
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• 제12권4호
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• pp.275-280
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• 2008

We propose a method generating elemental images for the integral imaging using 4-step phaseshifting digital holography. Phase shifting digital holography is a way recording the digital hologram by changing the phase of the reference beam and extracting the complex field of the object beam. Since all 3D information is captured by phase-shifting digital holography, the elemental images for any specifications of the lens array can be generated from single phase-shifting digital holography. In experiment, phase-shifting is achieved by rotating half- and quarter- wave plates and the resultant interference patterns are captured by a $3272{\times}2469$ pixel CCD camera with $27{\mu}m{\times}27{\mu}m$ pixel size.