• Proceedings of the Korea Electromagnetic Engineering Society Conference
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• 2005.11a
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• pp.131-136
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• 2005

UWB is the most spotlighted wireless technology that transmits data at very high rates using low power over a wide spectrum of frequency band. UWB technology makes it possible to transmit data at rate over 100Mbps within 10 meters. To preserve important header information, MB-OFDM UWB adopts Reed-Solomon(23,17) code. In receiver, RS decoder needs high speed and low latency using efficient hardware. In this paper, we suggest the architecture of RS decoder for MB-OFDM UWB. We adopts Modified-Euclidean algorithm for key equation solver block which is most complex in area. We suggest pipelined processing cell for this block and show the detailed architecture of syndrome, Chien search and Forney algorithm block. At last, we show the hardware implementation results of RS decoder for ASIC implementation.

• Proceedings of the IEEK Conference
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• 2001.06a
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• pp.113-116
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• 2001

Reed-Solomon(RS) code is the most powerful burst error correcting code. In Ois paper, the architecture for the adaptive RS encoder adaptable for multi QoS requirements or time-varying channel environments has been designed. In the adaptive RS code, the message length k and the error correction capability t are allowed to be variable so that the block length n is also variable. We proposed the architecture of the adaptive RS encoder by designing the optimal structure of Galois fields multiplier with comparison of fixed multiplier and variable multiplier. The proposed architecture is implemented in VHDL and verified with the simulation tool

• The Journal of Korean Institute of Communications and Information Sciences
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• v.36 no.10A
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• pp.809-815
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• 2011

In this paper, we have proposed and implemented a novel architecture which can be used to effectively design the modified Euclidean (ME) algorithm for key equation solver (KES) block in high-speed Reed-Solomon (RS) decoder. With polynomial expressions of newly-defined state variables for controlling each processing element (PE), the proposed architecture has simple input/output signals and requires less hardware complexity because no degree computation circuits are needed. In addition, since each PE circuit is independent of the error correcting capability t of RS codes, it has the advantage of linearly increase of the hardware complexity of KES block as t increases. For comparisons, KES block for RS(255,239,8) decoder is implemented using Verilog HDL and synthesized with 0.13um CMOS cell library. From the results, we can see that the proposed architecture can be used for a high-speed RS decoder with less gate count.

• Proceedings of the Korea Society of Information Technology Applications Conference
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• 2005.11a
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• pp.195-198
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• 2005

UWB is the most spotlighted wireless technology that transmits data at very high rates using low power over a wide spectrum of frequency band. UWB technology makes it possible to transmit data at rate over 100Mbps within 10 meters. To preserve important header information, MBOFDM UWB adopts Reed-Solomon(23,17) code. In receiver, RS decoder needs high speed and low latency using efficient hardware. In this paper, we suggest the architecture of RS decoder for MBOFDM UWB. We adopts Modified-Euclidean algorithm for key equation solver block which is most complex in area. We suggest pipelined processing cell for this block and show the detailed architecture of syndrome, Chien search and Forney algorithm block. At last, we show the hardware implementation results of RS decoder for ASIC implementation.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.6
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• pp.96-103
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• 2008

This paper proposes a new low-power and small-area Reed-Solomon decoder. The proposed Reed-Solomon decoder using a novel simplified form of the modified Euclid's algorithm can support low-hardware complexity and low-Power consumption for Reed-Solomon decoding. The simplified modified Euclid's algorithm uses new initial conditions and polynomial computations to reduce hardware complexity, and thus, the implemented architecture consisting of 3r basic cells has the lowest hardware complexity compared with existing modified Euclid's and Berlekamp-Massey architectures. The Reed-Solomon decoder has been synthesized using the $0.18{\mu}m$ Samsung standard cell library and operates at 370MHz and its data rate supports up to 2.9Gbps. For the (255, 239, 8) RS code, the gate counts of the simplified modified Euclid's architecture and the whole decoder excluding FIFO memory are only 20,166 and 40,136, respectively. Therefore, the proposed decoder can reduce the total gate count at least 5% compared with the conventional DCME decoder.

• Journal of Communications and Networks
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• v.9 no.3
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• pp.265-273
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• 2007

This paper expands an analytical performance model of 802.11 to accurately estimate throughput and energy demand of 802.11-based wireless sensor network (WSN) when sensor nodes employ Reed-Solomon (RS) codes, one of block forward error correction (FEC) techniques. This model evaluates these two metrics as a function of the channel bit error rate (BER) and the RS symbol size. Since the basic recovery unit of RS codes is a symbol not a bit, the symbol size affects the WSN performance even if each packet carries the same amount of FEC check bits. The larger size is more effective to recover long-lasting error bursts although it increases the computational complexity of encoding and decoding RS codes. For applying the extended model to WSNs, this paper collects traffic traces from a WSN consisting of two TIP50CM sensor nodes and measures its energy consumption for processing RS codes. Based on traces, it approximates WSN channels with Gilbert models. The computational analyses confirm that the adoption of RS codes in 802.11 significantly improves its throughput and energy efficiency of WSNs with a high BER. They also predict that the choice of an appropriate RS symbol size causes a lot of difference in throughput and power waste over short-term durations while the symbol size rarely affects the long-term average of these metrics.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.31A no.9
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• pp.34-43
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• 1994

The unequal symbol error probability of TCM(trellis coded modulation) is analyzed and applied to the derivation of bit error probability of /RS/Trellis concatenated coded-modulation system. An upper bound of the symbol error probability of TCM concatenated with RS code is obtained by exploiting the unequal symbol error probability of TCM, and it is applied to the derivation of the upper bound of the bit error probability of the RS/Trellis concatenated coded-modulation system. Our upper bounds of the concatenated codes are tighter than the earlier established other upper bounds.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.7
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• pp.1202-1207
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• 2006

In this paper we analyze the performance improvement of the M-ary FSK systems for low power and low data rate applications. This contribution presents a unified analysis of its MRC diversity, uncoded and performance in A WGN, m=2, m=3, Rayleigh and one sided Gaussian fading channels using optimum noncoherent demodulation with Reed-Solomon(RS) codes. The results of this paper should be useful as benchmarks of obtainable performance and as a reference for validating the results of simulation studies when slow fading models are applicable.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.49 no.5
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• pp.15-20
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• 2012

In this paper, we show new method to find the error locations of received Reed-Solomon code word. New design is much faster and has much simpler logic circuit than the former design method. This optimization was possible by very simplified square/$X^4$ calculating circuit, parallel processing and not using the very complex Divider. The Reed Solomon decoder using this new Chien Machine can be applicated for data protection of almost all digital communication and consumer electronic devices.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.30B no.11
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• pp.17-26
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• 1993

In this paper, a VlSI architecture for Reed-Solomon (RS) decoder based on the Berlekamp algorithm is proposed. The proposed decoder provided both erasure and error correcting capability. In order to reduc the chip area, we reformulate the Berlekamp algorithm. The proposed algorithm possesses a recursive structure so that the number of cells for computing the errata locator polynomial can be reduced. Moreover, in our approach, only one finite field multiplication per clock cycle is required for implementation, provided an improvement in the decoding speed, and the overall architecture features parallel and pipelined structure, making a real time decoding possible. From the performance evaluation, it is concluded that the proposed VLSI architecture is more efficient in terms of VLSI implementation than the rcursive architecture based on the Euclid algorithm.