• Proceedings of the KIEE Conference
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• 1999.07g
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• pp.3212-3214
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• 1999

RS(Reed-Solomon)부호는 오류 정정을 위한 채널 코딩기법중의 하나로 특히 연집 오류에 대해 강한 특성을 갖고 있으며, CD-P(Compact Disc Player), DAT(Digital Audio Tape). VTR, DVD(Digital Video Disc), 디지탈 TV 디코더등에서 사용되고 있다. 본 논문은 Galois Field, GF[$2^8$]상에서 (204. 188. 8)의 규격을 갖는 디지탈 TV용 RS 복호기의 구현에 관한 연구로 8개의 심볼 오류까지 정정 가능하다. 오증 계산은 16개의 오증 계산셀로 구성되어 지며, 오류 위치 다항식을 계산하는데 있어서는 Berlekamp-Massey 알고리즘을 사용한다. VHDL로 설계되어 Synopsys를 이용하여 검증 및 합성하였다.

• ETRI Journal
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• v.38 no.4
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• pp.612-621
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• 2016

A new time-domain decoder for Reed-Solomon (RS) codes is proposed. Because this decoder can correct both errors and erasures without computing the erasure locator, errata locator, or errata evaluator polynomials, the computational complexity can be substantially reduced. Herein, to demonstrate this benefit, complexity comparisons between the proposed decoder and the Truong-Jeng-Hung and Lin-Costello decoders are presented. These comparisons show that the proposed decoder consistently has lower computational requirements when correcting all combinations of ${\nu}$ errors and ${\mu}$ erasures than both of the related decoders under the condition of $2{\nu}+{\mu}{\leq}d_{\min}-1$, where $d_{min}$ denotes the minimum distance of the RS code. Finally, the (255, 223) and (63, 39) RS codes are used as examples for complexity comparisons under the upper bounded condition of min $2{\nu}+{\mu}=d_{\min}-1$. To decode the two RS codes, the new decoder can save about 40% additions and multiplications when min ${\mu}=d_{min}-1$ as compared with the two related decoders. Furthermore, it can also save 50% of the required inverses for min $0{\leq}{\mu}{\leq}d_{\min}-1$.

• JSTS:Journal of Semiconductor Technology and Science
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• v.10 no.3
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• pp.193-202
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• 2010

This paper presents a high-speed low-complexity pipelined Reed-Solomon (RS) (255,239) decoder using pipelined reformulated inversionless Berlekamp-Massey (pRiBM) algorithm and its folded version (PF-RiBM). Also, this paper offers efficient pipelining and folding technique of the RS decoders. This architecture uses pipelined Galois-Field (GF) multipliers in the syndrome computation block, key equation solver (KES) block, Forney block, Chien search block and error correction block to enhance the clock frequency. A high-speed pipelined RS decoder based on the pRiBM algorithm and its folded version have been designed and implemented with 90-nm CMOS technology in a supply voltage of 1.1 V. The proposed RS(255,239) decoder operates at a clock frequency of 700 MHz using the pRiBM architecture and also operates at a clock frequency of 750 MHz using the PF-RiBM, respectively. The proposed architectures feature high clock frequency and low-complexity.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.40 no.8
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• pp.1477-1484
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• 2015

In this paper, a novel reversible data hiding by using Reed-Solomon (RS) code is proposed for efficient transmission in encryption image. To increase the recovery of data from encrypted image, RS codes are used to encode messages, and then the codewords can be embedded into encrypted image according to encryption key. After receiving encrypted image which embeds the codewords, the receiver firstly decryptes the encrypted image using the encryption key and get metric about codewords containing messages. According to recovery capability of RS codes, better estimation of message is done in data hiding system. Simulation results about two images and two RS codes show that the performances of the proposed schemes are better than ones of the reference scheme.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.5B
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• pp.966-973
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• 2000

In this paper, we propose a novel RS decoder design yielding smallr circuit size shorter coding latency. The proposed architecture of RS decoder has the following two features. First, circuit size reduced by using Euclid algorithm with mutual operation between cells. Second, coding latency is reduced by using higher frequency than syndrome and error value calculation block. We performed simulation with C language and MATLAB in order to verify the decoding algorithm and implemented using FPGA chips in VHDL.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.18 no.10
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• pp.1495-1507
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• 1993

In this paper, an implementation of RS (Reed-Solomon) code decoder for CDP (Compact Disc Player) using microprogramming method is presented. In this decoding strategy, the equations composed of Newton's identities are used for computing the coefficients of the error locator polynomial and for checking the number of erasures in C2(outer code). Also, in C2 decoding the values of erasures are computed from syndromes and the results of C1(inner code) decoding. We pulled up the error correctability by correcting 4 erasures or less. The decoder contains an arithmetic logic unit over GF(28) for error correcting and a decoding controller with programming ROM, and also microinstructions. Microinstructions are used for an implementation of a decoding algorithm for RS code. As a result, it can be easily modified for upgrade or other applications by changing the programming ROM only. The decoder is implemented by the Logic Level Modeling of Verilog HDL. In the decoder, each microinstruction has 14 bits( = 1 word), and the size of the programming ROM is 360 words. The number of the maximum clock-cycle for decoding both C1 and C2 is 424.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.36 no.11C
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• pp.649-654
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• 2011

In this paper, we show new method to find number of errors in the Reed-Solomon decoder. New design is much faster and has much simpler logic circuit than the former design method. This optimization was possible by very simplified square calculating circuit and parallel processing. The microcontroller of this Reed Solomon decoder can be used for data protection of almost all digital communication and consumer electronic devices.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.36 no.1C
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• pp.8-13
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• 2011

In this paper, we show new method to find error locations of 2 eight bit symbol errors for 2 error correcting Reed-Solomon decoder. New design is much faster and has much simpler logic circuit than the former design method. This optimization was possible by partitioning the 8 bit operations into 4 bit arithgmatic and logic operations. This Reed Solomon decoder can be used for data protection of almost all digital communication and consumer electronic devices.

• The Transactions of the Korea Information Processing Society
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• v.7 no.1
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• pp.306-312
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• 2000

In this paper, the efficient architecture of small Reed-solomon architecture is suggested. Here, 3-stage pipeline is adopted. In decoding, error-location polynomials are obtained by BMA using fast iteration method, and syndrome polynomials, where calculation complexity is required, are obtained by parallel calculation using ROM table, and the roots of error location polynomial are calculated by ROM table using Chein search algorithm. In the suggested decoder, it is confirmed that 3 symbol random errors can be corrected and 124Mbps decoding rate is obtained using 25 Mhz system clock.

• Journal of Navigation and Port Research
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• v.28 no.1
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• pp.23-29
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• 2004

This paper deals with Reed-Solomon Coding for EUROFIX system EUROFIX is an integrated navigation and communication system, which combines Differential GNSS and Loran-C EUROFIX transmits DGNSS(Differential Global Navigation Satellite Systems) (data by pulse position modulation of Loran-C pulses. Loran-C system is regarded as a satellite backup system in recent. And now, it is important to detect and correct much errors in communication systems. Error corrections or correction algorithm is actively studied nowadays because of this. In this paper, we study and design encoder and decoder of Reed Solomon Code using Finite Galois Field Fourier Transformation for error corrections in EUROFIX data transmission. Through extensive simulation, the designed Reed Solomon code is shown to be effective for error correction in EUROFIX data transmission.