• Proceedings of the KIEE Conference
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• 2003.11c
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• pp.806-809
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• 2003

Digital controllers have developed rapidly in recent years. This paper describes the synchronized signal generation circuits for control of Multiple Controllers and test results. Also this paper describes configuration and functions of digital excitation system. The digital excitation system is made up of triple redundancy and has control and protection functions.

• KIPS Transactions on Computer and Communication Systems
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• v.3 no.5
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• pp.129-140
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• 2014

BIST(Built-in self test) is to detect various faults of the existing memory and BIRA(Built-in redundancy analysis) is to repair detected faults by allotting spare. Also, BISR(Built-in self repair) which integrates BIST with BIRA, can enhance the whole memory's yield. However, the previous methods were suggested for RAM and are difficult to diagnose disturbance that is NAND-type flash memory's intrinsic fault when used for the NAND-type flash memory with different characteristics from RAM's memory structure. Therefore, this paper suggests a BISD(Built-in self diagnosis) to detect disturbance occurring in the NAND-type flash memory and to diagnose the location of fault, and BISR to repair faulty blocks.

• Journal of Information Display
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• v.10 no.1
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• pp.6-15
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• 2009

In this paper, a new approach is proposed for the efficient generation of computer-generated holograms (CGHs) using the spatially redundant data on a 3D object and the novel look-up table (N-LUT) method. First, the pre-calculated N-point principle fringe patterns (PFPs) were calculated using the 1-point PFP of the N-LUT. Second, spatially redundant data on a 3D object were extracted and re-grouped into the N-point redundancy map using the run-length encoding (RLE) method. Then CGH patterns were generated using the spatial redundancy map and the N-LUT method. Finally, the generated hologram patterns were reconstructed. In this approach, the object points that were involved in the calculation of the CGH patterns were dramatically reduced, due to which the computational speed was increased. Some experiments with a test 3D object were carried out and the results were compared with those of conventional methods.

• Steel and Composite Structures
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• v.42 no.1
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• pp.139-149
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• 2022

To simplify the design and reduce the construction cost of traditional multi-girder structural systems, twin I-girder structures are widely used in many countries in recent years. Due to the concern on post-fracture redundancy, however, twin girder bridges are currently classified as fracture critical structures in AASHTO specifications for highway bridges. To investigate the after-fracture behavior of such structures, a composite steel and concrete twin girder specimen was built and an artificial fracture through the web and the bottom flange was created on one main girder. The static loading test was performed to investigate its mechanical performance after a severe fracture occurred on the main girder. Applied load and vertical displacement curves, and the applied load versus strain relationships at key sections were measured. To investigate the load distribution and transfer capacities between two steel girders, the normal strain development on crossbeams was also measured during the loading test. In addition, both shear and normal strains of studs were also measured in the loading test to explore the behavior of shear connectors in such bridges. The functions and structural performance of structural members and possible load transfer paths after main girder fractures in such bridges were also discussed. The test results indicate in this study that a typical twin I-girder can resist a general fracture on one of its two main girders. The presented results can provide references for post-fracture performance and optimization for the design of twin I-girder bridges and similar structures.

• Journal of Institute of Control, Robotics and Systems
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• v.10 no.1
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• pp.1-9
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• 2004

Inertial navigation system with hardware redundancy must use FDI(Fault Detection and Isolation) method to remove the influence of faulty sensors. Until now, several FDI methods such as PSA(Parity Space Approach), GLT(Generalized Likelihood ratio Test) and OPT(Optimal Parity vector Test) method are generally used. However, because these FDI methods only consider the situation that the system has one faulty sensor, these methods cannot be directly adapted for the system with two faulty sensors. To solve this problem, in this paper, PSA method is analyzed and based on this result, new FDI method called EPSA is proposed to consider a detection and an isolation of two faulty sensors in inertial navigation system.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.34C no.8
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• pp.39-48
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• 1997

The fast redundancy identification is required to perform an efficient test pattern genration. Due to the reconvergent fanouts which make the dependency among objectives and the fault propagation blocking, there may exist redundnat faults in the cirucit. This paper presents the isomorphism identification and the pseudo dominator algorithms which are useful to identify redundant faults in combinational circuits. The isomorphism identification algorithm determines whether mandatory objectives required for fault detection cannot be simultaneously satisfied from primary input assignments or not using binary decision diagrma. The pseudo dominator algorithm determines whether faults propagation is possible or not by considering all paths at a given fanout node. Several experiments using ISCAS 85 benchmark circuits demonstrate the efficiency and practicability of the algorithms.

• ETRI Journal
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• v.32 no.4
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• pp.642-644
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• 2010

With the rapid increase occurring in both the capacity and density of memory products, test and repair issues have become highly challenging. Memory repair is an effective and essential methodology for improving memory yield. An SoC utilizes built-in redundancy analysis (BIRA) with built-in self-test for improving memory yield and reliability. This letter proposes a new heuristic algorithm and new hardware architecture for the BIRA scheme. Experimental results indicate that the proposed algorithm shows near-optimal repair efficiency in combination with low area and time overheads.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.34 no.10B
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• pp.1076-1085
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• 2009

In this paper, a new method for efficient computation of CGH patterns for 3-D video images is proposed by combined use of temporal redundancy and look-up table techniques. In the conventional N-LT method, fringe patterns for other object points on that image plane can be obtained by simply shifting these pre-calculated PFP (Principle Fringe Patterns). But there have been many practical limitations in real-time generation of 3-D video holograms because the computation time required for the generation of 3-D video holograms must be massively increased compared to that of the static holograms. On the other hand, as ordinary 3-D moving pictures have numerous similarities between video frames, called by temporal redundancy, and this redundancy is used to compress the video image. Therefore, in this paper, we proposed the efficient hologram generation method using the temporal redundancy of 3-D video image and N-LT method. To confirm the feasibility of the proposed method, some experiments with test 3-D videos are carried out, and the results are comparatively discussed with the conventional methods in terms of the number of object points and computation time.

• The Journal of Information Technology
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• v.3 no.3
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• pp.57-65
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• 2000

We have proposed BIST method and circuit for embedded 16M SDRAM with logic. It can test the AC parameter of embedded 16M SDRAM using the BIST circuit capable of detecting the address of a fail cell of a 16M SDRAM installed in an Merged Memory with Logic(MML) generating the information of repair for redundancy circuit. The function and AC parameter of the embedded memory can also be tested using the proposed BIST method. The total gate of the BIST circuit is approximately 4,500 in the case of synthesizing by $0.25\mu\textrm{m}$ cell library. and verify the result of Verilog simulation. The test time of each one AC parameter is about 200ms using 2Y-March 14N algorithm.

• Industrial Engineering and Management Systems
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• v.4 no.1
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• pp.94-101
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• 2005

This paper presents the first known application of a meta-heuristic algorithm, variable neighbourhood descent (VND), to the redundancy allocation problem (RAP). The RAP, a well-known NP-hard problem, has been the subject of much prior work, generally in a restricted form where each subsystem must consist of identical components. The newer meta-heuristic methods overcome this limitation and offer a practical way to solve large instances of the relaxed RAP where different components can be used in parallel. The variable neighbourhood descent method has not yet been used in reliability design, yet it is a method that fits perfectly in those combinatorial problems with potential neighbourhood structures, as in the case of the RAP. A variable neighbourhood descent algorithm for the RAP is developed and tested on a set of well-known benchmark problems from the literature. Results on 33 test problems ranging from less to severely constrained conditions show that the variable neighbourhood descent method provides comparable solution quality at a very moderate computational cost in comparison with the best-known heuristics. Results also indicate that the VND method performs with little variability over random number seeds.