• Title/Summary/Keyword: Reduction device

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Development of Interconnect Process Technology for 5 nm Technology Nodes (5 nm 급 반도체 배선 공정 기술 개발)

  • Choi, Eunmi;Pyo, Sung Gyu
    • Journal of the Microelectronics and Packaging Society
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    • v.23 no.4
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    • pp.25-29
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    • 2016
  • The semiconductor industry has been developed mainly by micronization process due to many advantages of miniaturization of devices. Mass production of semiconductors of 10 nm class has been started recently, and it is expected that the technology generation of 5 nm & 7 nm technology will come. However, excessive linewidth reduction affects physical limits and device reliability. To solve these problems, new process technology development and new concept devices are being studied. In this review, we introduce the next generation technology and introduce the advanced research for the new concept device.

A Study on the Daily Inspection of the Rolling-stocks (철도차량 일상검수 주기 및 방법에 관한 연구)

  • Yu, Yang-Ha;Lee, Nak-Young;Kim, Ho-Soon
    • Proceedings of the KSR Conference
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    • 2010.06a
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    • pp.1642-1649
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    • 2010
  • At present, KORAIL is in the middle of renovating. All steps exert great effort at cost reduction and a profit improvement. Especially to improve maintenance method and inspection period at the rolling-stock division lots of research is under progress. Daily inspection of rolling stocks is to operate the rolling stock normally. Daily inspection items are driving control device, coupling device, brake system, water system and air conditioning system, electrical system etc. Half of the maintenance manpower are inputted at daily inspection. Strengthens the quality and optimize the proportion of daily inspection are urgent problem. Daily inspection period extension aim is as follows. KTX from 3,500km to 5,000km, passenger car from 1st to 3,500km, new style electric locomotive from 2nd to 5,000km, the diesel locomotive is 2,800km from 1,200km. In this paper, the optimal daily inspection period and methods are considered including expected problem and counter measures.

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Analysis of Noise Reduction Performance for Noise Cut Transformer (Noise Cut Transformer의 노이즈 억제성능 분석)

  • Lee, Jae-Bok;Huh, Chang-Su;Lee, Ki-Chul;Myung, Sung-Ho;Ha, Tae-Hyun
    • Proceedings of the KIEE Conference
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    • 1996.07c
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    • pp.1784-1786
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    • 1996
  • It is necessary to eliminate the broad band noise which frequency is in a few kHz to MHz in the AC line to supply the power to electrical and electronic control equipments. Because this kind of noise could damage the device or could be a source of malfunction, many devices like a filter and surge suppressor are developed to cut off the noise. But those device could not disconnected from the power line, so it remain some problem and on be used in limited area, In this paper, we present performance test results NCT(noise Cut Transformer) with excellent performance for reducing the high frequency noise and surge existing in the power line.

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Development of Active Matrix Cathodes Composed of a-Si:H TFTs and Gated Molybdenum Field Emitter Arrays

  • Chung, Choong-Heui;Song, Yoon-Ho;Hwang, Chi-Sun;Ahn, Seong-Deok;Kim, Bong-Chul;Cho, Young-Rae;Lee, Jin-Ho;Cho, Kyoung-Ik
    • 한국정보디스플레이학회:학술대회논문집
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    • 2002.08a
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    • pp.1020-1023
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    • 2002
  • We successfully developed a-Si TFT controlled active matrix cathode (AMC) with gated Mo emitters. Also, we could remove emitter failures of the AMC through a novel surface treatment of Mo-tips, which indicates reduction of $MoO_3$ or chemical wet etching of $MoO_3$ by surface treatment. Transient behaviors of the AMC are strongly dependent on not only DC characteristics of device but also the device structure. Brightness and gray scale were well realized by low-voltage scan and data signals addressed to a-Si TFTs.

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Dimensional Stability of an Imprinted Microoptic Waveguide (임프린트 기반 마이크로 광도파로의 변형 특성 연구)

  • Ryu, Jin-Hwa;Kim, Chang-Seok;Jeong, Myung-Yung
    • Journal of the Korean Society for Precision Engineering
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    • v.25 no.11
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    • pp.100-106
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    • 2008
  • We have studied the characteristic changes of optical device using imprint lithography. An imprinted structure is inherently involved in residual stress due to the temperature and the pressure cycle during fabrication process. A structure with residual stress undergoes stress relaxation, which leads io dimensional change. Therefore, annealing processes was performed to reduce the residual stress of imprinted polymer channel. Reduction of residual stress was confirmed through dimensional change, birefringence, and the mechanical properties. We have fabricated an optical device, and it saw the optical intensity changes within 0.1% for 1 month.

A study on the development of noise reducing device installed on the top of noise barrier for 400km/h class high-speed railroad (400km/h급 고속철도 소음저감용 방음벽 상단장치 개발에 관한 연구)

  • Yoon, Je Won;Kim, Yonng Chan;Jang, Kang Seok;Hong, Bynng Kook;Eum, Young-Ki
    • Proceedings of the Korean Society for Noise and Vibration Engineering Conference
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    • 2013.04a
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    • pp.708-713
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    • 2013
  • 본 연구의 목적은 400km/h 급 고속철도 소음저감용 방음벽 상단장치를 개발하기 위함이다. 이를 위해 우선 현장에서의 소음측정을 통한 400km/h 급 고속철도(HEMU) 및 300km/h 급 KTX의 주파수특성을 분석하였다. 그리고, 해석적 기법(BEM) 및 시작품 제작을 통한 실내실험을 수행하여 3dB(A) 이상의 소음을 저감시킬 수 있는 상단장치를 설계하였다. 마지막으로, 상단장치 시작품을 제작하여 옥외시험실에서의 성능시험을 수행하였으며, 고속철도의 주파수특성을 반영한 상단장치 설치 전후의 감음량을 평가하였다.

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Development of Directional Digital Hearing Aid Performance Testing System (지향성 보청기 성능 검사 장치 개발)

  • Jang, Soon-Suck;Kwon, You-Jung;Lee, Je-Hyeong
    • Transactions of the Korean Society for Noise and Vibration Engineering
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    • v.16 no.1 s.106
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    • pp.81-88
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    • 2006
  • The most recent trend on digital hearing aid is to increase the ratio of signal to noise by directivity or to develop noise reduction algorithm inside DSP IC chip. This paper designed, fabricated and tested a digital hearing aid directivity testing device in which a micro-mouse-like the stepping motor with a speaker rotates around an examinant. Both ears of the examinant were fixed with ITE hearing aids in order to respond to receiving sound. The experimental results were compared with those of a boundary element method program for verification. The diameter of the directivity testing device was 2 m and the micro-mouse was precisely controlled by PICBASIC micro processor.

A Study on the Characteristics of PSA Device using RTA Process and Trench Technology (RTA 공정 및 Trench 격리기술을 사용한 PSA 바이폴라 소자의 특성 연구)

  • Koo, Yong-Seo;Kang, Sang-Won;An, Chul
    • Journal of the Korean Institute of Telematics and Electronics A
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    • v.28A no.9
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    • pp.743-751
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    • 1991
  • This paper presents the 1.5\ulcorner PSA bipolar device which establishes the performance improvement such as the reduction of emitter resistance and substrate junction capacitance. To achieve the above electrical characteristics, RTA process and trench isolation technology were adapted. The emitter resistance and substrate capacitance of npn transistor having 1.5$[\times}6{\mu}m^{2}$emitter area was measured with 63$\Omega$and 28fF, respectively. The minimum propagation delay time shows 121ps at 0.7mW from the measurement of 31 stage ring oscillator.

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Dependence of deep submicron CMOSFET characteristics on shallow source/drain junction depth (얕은 소오스/드레인 접합깊이가 deep submicron CMOSFET 소자 특성에 미치는 영향)

  • 노광명;고요환;박찬광;황성민;정하풍;정명준
    • Journal of the Korean Institute of Telematics and Electronics A
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    • v.33A no.4
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    • pp.112-120
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    • 1996
  • With the MOsES (mask oxide sidewall etch scheme)process which uses the conventional i-line stepper and isotropic wet etching, CMOSFET's with fine gate pattern of 0.1.mu.m CMOSFET device, the screening oxide is deposited before the low energy ion implantation for source/drain extensions and two step sidewall scheme is adopted. Through the characterization of 0.1.mu.m CMOSFET device, it is found that the screening oxide deposition sheme has larger capability of suppressing the short channel effects than two step sidewall schem. In cse of 200.angs.-thick screening oxide deposition, both NMOSFET and PMOSFET maintain good subthreshold characteristics down to 0.1.mu.m effective channel lengths, and show affordable drain saturation current reduction and low impact ionization rates.

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Palmprint Authentication Algorithm using the Basis Vector (기저벡터를 이용한 장문 인증 알고리즘)

  • Noh, Jin-Soo;Baek, Hui-Chang;Rhee, Kang-Hyeon
    • Proceedings of the IEEK Conference
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    • 2006.06a
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    • pp.757-758
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    • 2006
  • In this paper, the palmprint classification and recognition method based on PCA (Principal Components Analysis) using the dimension reduction of singular vector is proposed. And the 135dpi palmprint image which is obtained by the palmprint acquisition device is used for the effectual palmprint recognition system. The proposed system consists of the palmprint acquisition device, DB generation algorithm and the palmprint recognition algorithm. The palmprint recognition step is limited 2 times. As a results, GAR and FAR are 98.5% and 0.036%.

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