• Journal of Advanced Marine Engineering and Technology
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• 제37권1호
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• pp.121-126
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• 2013

교류기기의 속도 및 토크 제어시스템에서 전력변환장치로 사용되는 싸이클로컨버터는 저속에서 토크가 크고 제어가 간단한 장점을 가지고 있다. 또한, 정류기, 직류링크부, 인버터가 설치되지 않으므로 시스템이 간단하고 대전력 시스템에 적합하다. 현재 사용되고 있는 대형선박의 추진전동기의 구동용 전력변환장치를 싸이클로컨버터로 변경하면 시스템이 간단해지므로 설치비용을 크게 감소시킬 수 있다. 하지만 기존의 싸이클로컨버터는 전력 반도체소자의 고속 스위칭에 의한 손실이 크고 출력 전압파형이 왜곡되어서 고조파 성분이 증가하게 된다. 본 논문에서는 이러한 단점을 개선하기 위해서 1차측에 위상이 다른 2개의 입력단과 2차측에 1개의 출력단으로 구성되는 상천이 필터를 설치한다. 위상이 다른 2개의 전압파형이 더해져서 2차측으로 변압됨으로써 전압파형이 정현파에 가깝게 출력된다. 그로 인해 추진전동기에 입력되는 전압파형이 개선되고 총고조파왜형율도 크게 감소한다.

• Journal of Power Electronics
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• 제7권2호
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• pp.146-158
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• 2007

A multi-pulse GTO based voltage source converter (VSC) topology together with a fundamental frequency switching mode of gate control is a mature technology being widely used in static synchronous compensators (STATCOMs). The present practice in utility/industry is to employ a high number of pulses in the STATCOM, preferably a 48-pulse along with matching components of magnetics for dynamic reactive power compensation, voltage regulation, etc. in electrical networks. With an increase in the pulse order, need of power electronic devices and inter-facing magnetic apparatus increases multi-fold to achieve a desired operating performance. In this paper, a competitive topology with a fewer number of devices and reduced magnetics is evolved to develop an 18-pulse, 2-level $\pm$ 100MVAR STATCOM in which a GTO-VSC device is operated at fundamental frequency switching gate control. The inter-facing magnetics topology is conceptualized in two stages and with this harmonics distortion in the network is minimized to permissible IEEE-519 standard limits. This compensator is modeled, designed and simulated by a SimPowerSystems tool box in MATLAB platform and is tested for voltage regulation and power factor correction in power systems. The operating characteristics corresponding to steady state and dynamic operating conditions show an acceptable performance.

• Journal of Power Electronics
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• 제16권2호
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• pp.532-541
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• 2016

A single-phase asymmetrical cascaded multilevel inverter is introduced with the goal of increasing power quality with the reduction of power in insulated-gate bipolar transistor (IGBT) switches. In the present work, the proposed inverter topology is analyzed and generalized with respect to different proposed algorithms for choosing different voltage source values. To prove the advantages of the proposed inverter, a case study involving a 17-level inverter is conducted. The simulation and experimental results with reduced THD are also presented and compared with the MATLAB/SIMULINK simulation results. Finally, the proposed topology is compared with different multilevel inverter topologies available in the literature in terms of the number of IGBT switches required with respect to the number of levels generated in the output of inverter topologies.

• Journal of Power Electronics
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• 제11권5호
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• pp.677-687
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• 2011

In this paper a cycloconverter-type high frequency transformer link inverter with a reduced switch count is analyzed and designed. The proposed topology consists of an H-bridge inverter at the transformer's primary side and a cycloconverter with three bidirectional switches at the secondary. All of the switches of the cycloconverter operate in non-resonant zero voltage and zero current switching modes. To overcome a high voltage surge problem resulting from the transformer leakage inductance, phase angle control based on natural commutation is employed. The effectiveness of the proposed inverter is verified by constructing s 750W prototype. Experimentally, the inverter is able to supply a near sinusoidal output voltage with a total harmonic distortion of less than 1%. For comparison, a PSpice simulation of the inverter is also carried out. It was found that the experimental results are in very close agreement with the simulation.

• Journal of Power Electronics
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• 제15권4호
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• pp.951-963
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• 2015

In this paper, a new symmetric multilevel inverter is proposed. A simple structure for the cascaded multilevel inverter topology is also proposed, which produces a high number of levels with the application of few power electronic devices. The symmetric multilevel inverter can generate 2n+1 levels with a reduced number of power switches. The basic unit is composed of a single and double source unit (SDS-unit). The application of this SDS-unit is for reducing the number of power electronic components like insulated gate bipolar transistors, freewheeling diodes, gate driver circuits, dc voltage sources, and blocked voltages by switches. Various new algorithms are recommended to determine the magnitude of dc sources in a cascaded structure. Furthermore, the proposed topology is optimized for different goals. The proposed cascaded structure is compared with other similar topologies. For verifying the performance of the proposed basic symmetric and cascaded structure, results from a computer-based MATLAB/Simulink simulation and from experimental hardware are also discussed.

• Journal of Electrical Engineering and Technology
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• 제11권6호
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• pp.1674-1683
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• 2016

In this paper, a Finite Control Set Model Predictive Control (FCS-MPC) for a five level cascaded multilevel inverter (CMLI) with reduced switch topology is proposed. Five switches are used here instead of conventionally used eight switches. The main contribution of this paper is to make the MPC controller work for the reduced switch topology using only 19 voltage vectors in place of conventional 61 voltage vectors for a five level CMLI. This simplifies the execution of the MPC algorithm, paving a way for the significant reduction in the computational time. The controller makes use of the excellent ability of MPC to multitask, by adding one more objective which is to reduce the average switching frequency in addition to controlling the load current. This is especially important, since switching losses and therefore switching frequency is significant for high-power applications. The trade-off of this MPC is that the current is not as smooth as the 61 vector scheme, but well within the limits of IEEE standards. The results shown prove that this MPC works well in steady state and dynamic conditions too.

• Journal of Electrical Engineering and Technology
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• 제13권2호
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• pp.688-698
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• 2018

Quasi Z-Source Multilevel Inverter (QZMLI) topology has attracted grid connected Photovoltaic (PV) systems in recent days. So there is a remarkable research thrust in switching techniques and control strategies of QZMLI. This paper presents the mathematical analysis of Phase shift- Pulse Width Amplitude Modulation (PS-PWAM) for QZMLI and emphasizes on the advantages of the technique. The proposed technique uses the maximum and minimum envelopes of the reference waves for generation of pulses and proportion of it to generate shoot-through pulses. Hence, it results in maximum utilization of input voltage, lesser switching loss, reduced Total Harmonic Distortion (THD) of the output voltage, reduced inductor current ripple and capacitor voltage ripple. Due to these qualities, the QZMLI with PS-PWAM emerges to be the best suitable for PV based grid connected applications compared to Phase shift-Pulse Width Modulation (PS-PWM). The detailed math analysis of the proposed technique has been disclosed. Simulation has been performed for the proposed technique using MATLAB/Simulink. A prototype has been built to validate the results for which the pulses were generated using FPGA /SPARTAN 3E.

• 조명전기설비학회논문지
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• 제13권3호
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• pp.25-33
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• 1999

본 논문에서는 다이오드 정류기와 부스트 컨버터가 결합되 단상 PWM컨버터의 역률보상 및 고조파 저감 기법에 관하여 연구하였다. 일반적인 다이오드 정류기의 경우에서는 전원 입력측에 불연속 펄스 전류가 흘러서 역률의 저하 및 고조파 왜곡이 포함되어 다른 전원계통에 악영향을 주는 문제점이 있다. 이를 해결하기 위하여 본 논문에서는 3차 고조파가 주입된 PWM 기법을 사용하여 입력전류에서의 고조파왜곡이 감소되는 AC-DC 부스트 컨버트를 제안하였다. 이때의 부스트 컨버터는 스위칭 손실 및 회로구성이 용이한 불연속적전류모드 제어방식을 채용하였다. 스위칭 주파수가 5[kHz]인 컨버터를 구성하여 컴퓨터 시뮬레이션 및 실험을 행하였으며 그 결과 역률 보상 및 전 고조파 왜곡이 감소되었음을 확인하였다.

• 대한의용생체공학회:의공학회지
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• 제25권4호
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• pp.269-275
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• 2004

인체내부의 각 조직은 서로 다른 저항률(resistivity)분포를 가지며, 조직의 생리학적, 기능적 변화에 따라 임피던스가 변화한다. 본 논문에서는 주로 기능적 영상을 위한 임피던스 단층촬영 (EIT, electrical impedance tomography) 시스템의 설계와 구현 결과를 기술한다. EIT 시스템은 인체의 표면에 부착한 전극을 통해 전류를 주입하고 이로 인해 유기되는 전압을 측정하여, 내부 임피던스의 단층영상을 복원하는 기술이다. EIT 시스템의 개발에 있어서는 영상복원의 난해함과 아울러 측정시스템의 낮은 정확도가 기술적인 문제가 되고 있다. 본 논문은 기존 EIT 시스템의 문제점을 파악하고 디지털 기술을 이용하여 보다 정확도가 높고 안정된 시스템을 설계 및 제작하였다. 크기와 주파수 및 파형의 변화 가능한 50KHz의 정현파 전류를 인체에 주입하기 위해 필요한 정밀 정전류원을 설계하여 제작한 결과, 출력 파형의 고조파 왜곡(THD, total harmonic distortion)이 0.0029%이고 진폭 안정도가 0.022%인 전류를 출력 할 수 있었다. 또한, 여러개의 정전류원을 사용함으로써 채 널간 오차를 유발하던 기존의 시스템을 변경하여, 하나의 전류원에서 만들어진 전류를 각 채널로 스위칭하여 공급함으로써 이로 인한 오차를 줄였다. 주입전류에 의해 유기된 전압의 정밀한 측정을 위해 높은 정밀도를 갖는 전압측정기가 필요하므로 차동증폭기, 고속 ADC및 FPGA(field programmable gate array)를 사용한 디지털 위상감응복조기 (phase-sensitive demodulator )를 제작하였다. 이때 병렬 처리를 가능하게 하여 모든 전극 채널에서 동시에 측정을 수행 할 수 있도록 하였으며, 제작된 전압측정기의 SNR(signal-to-noise ratio)은 90dB 이다. 이러한 EIT 시스템을 사용하여 배경의 전해질 용액에 비해 두 배의 저항률을 가지는 물체(바나나)에 대한 기초적인 영상복원 실험을 수행하였다. 본 시스템은 16채널로 제작되었으나 전체를 모듈형으로 설계하여 쉽게 채널의 수를 늘릴 수 있는 장점을 가지고 있어서 향후 64채널 이상의 디지털 EIT시스템을 제작할 계획이며, 인체 내부의 임피던스 분포를 3차원적 으로 영상화하는 연구를 수행 할 예정이다.

• Journal of Power Electronics
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• 제15권3호
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• pp.670-684
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• 2015

The hybrid cascaded multilevel inverter (HCMLI) is a popular converter topology that is being increasingly used in high power medium voltage drives. The intricacy of the control technique for a HCMLI increases with the number of levels and due to fluctuating dc voltages. This paper presents a novel offline quadrant search based space vector modulation technique to synthesize a sinusoidal output from a dispersed pattern of voltage vectors due to different voltages in the auxiliary unit. Such an investigation has never been reported in the literature and it is being attempted for the first time. The method suggested distributes the voltage vectors for a reduced total harmonic distortion at minimal computation. In addition, the proposed algorithm determines the maximum modulation index in the linear modulation range in order to synthesize a sinusoidal output for both normal and abnormal vector patterns. It is better suited for a wide range of practical applications. It is particularly well suited for renewable source fed inverters which utilize large capacitor banks to maintain the dc link, which are prone to such slow fluctuations. The proposed quadrant search space vector modulation technique is simulated using MATLAB/SIMULINK and implemented using a Nexys-2 Spartan-3E FPGA for a developed prototype.