• Journal of Advanced Marine Engineering and Technology
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• v.37 no.1
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• pp.121-126
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• 2013

Cycloconverter used as a power conversion device in the speed and torque control system of AC machines has the advantage of a simple control and a large torque at low speed. In addition, because a rectifier, a DC link, and an inverter are not installed, this system is simple and suitable for large power system. If a power conversion device, which is currently used as a propulsion motor of large vessel, is changed into cycloconverter, the system is simplified and then the installation costs can be significantly reduced. However, conventional cycloconverter has the increased harmonics because the power loss is large and the waveform of output voltage is distorted, due to the high-speed switching of power semiconductor devices. In order to improve these shortcomings, this paper describes a phase shifting filter which is composed of two inputs with different phases in the primary side and one output in the secondary one. As the voltage waveforms with two different phases are added and transformed into the secondary side, these outputs are close to sinusoidal waves. Thereby the voltage waveforms, which are applied to the propulsion motors, are improved and total harmonic distortions (THDs) are significantly reduced.

• Journal of Power Electronics
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• v.7 no.2
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• pp.146-158
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• 2007

A multi-pulse GTO based voltage source converter (VSC) topology together with a fundamental frequency switching mode of gate control is a mature technology being widely used in static synchronous compensators (STATCOMs). The present practice in utility/industry is to employ a high number of pulses in the STATCOM, preferably a 48-pulse along with matching components of magnetics for dynamic reactive power compensation, voltage regulation, etc. in electrical networks. With an increase in the pulse order, need of power electronic devices and inter-facing magnetic apparatus increases multi-fold to achieve a desired operating performance. In this paper, a competitive topology with a fewer number of devices and reduced magnetics is evolved to develop an 18-pulse, 2-level $\pm$ 100MVAR STATCOM in which a GTO-VSC device is operated at fundamental frequency switching gate control. The inter-facing magnetics topology is conceptualized in two stages and with this harmonics distortion in the network is minimized to permissible IEEE-519 standard limits. This compensator is modeled, designed and simulated by a SimPowerSystems tool box in MATLAB platform and is tested for voltage regulation and power factor correction in power systems. The operating characteristics corresponding to steady state and dynamic operating conditions show an acceptable performance.

• Journal of Power Electronics
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• v.16 no.2
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• pp.532-541
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• 2016

A single-phase asymmetrical cascaded multilevel inverter is introduced with the goal of increasing power quality with the reduction of power in insulated-gate bipolar transistor (IGBT) switches. In the present work, the proposed inverter topology is analyzed and generalized with respect to different proposed algorithms for choosing different voltage source values. To prove the advantages of the proposed inverter, a case study involving a 17-level inverter is conducted. The simulation and experimental results with reduced THD are also presented and compared with the MATLAB/SIMULINK simulation results. Finally, the proposed topology is compared with different multilevel inverter topologies available in the literature in terms of the number of IGBT switches required with respect to the number of levels generated in the output of inverter topologies.

• Journal of Power Electronics
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• v.11 no.5
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• pp.677-687
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• 2011

In this paper a cycloconverter-type high frequency transformer link inverter with a reduced switch count is analyzed and designed. The proposed topology consists of an H-bridge inverter at the transformer's primary side and a cycloconverter with three bidirectional switches at the secondary. All of the switches of the cycloconverter operate in non-resonant zero voltage and zero current switching modes. To overcome a high voltage surge problem resulting from the transformer leakage inductance, phase angle control based on natural commutation is employed. The effectiveness of the proposed inverter is verified by constructing s 750W prototype. Experimentally, the inverter is able to supply a near sinusoidal output voltage with a total harmonic distortion of less than 1%. For comparison, a PSpice simulation of the inverter is also carried out. It was found that the experimental results are in very close agreement with the simulation.

• Journal of Power Electronics
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• v.15 no.4
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• pp.951-963
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• 2015

In this paper, a new symmetric multilevel inverter is proposed. A simple structure for the cascaded multilevel inverter topology is also proposed, which produces a high number of levels with the application of few power electronic devices. The symmetric multilevel inverter can generate 2n+1 levels with a reduced number of power switches. The basic unit is composed of a single and double source unit (SDS-unit). The application of this SDS-unit is for reducing the number of power electronic components like insulated gate bipolar transistors, freewheeling diodes, gate driver circuits, dc voltage sources, and blocked voltages by switches. Various new algorithms are recommended to determine the magnitude of dc sources in a cascaded structure. Furthermore, the proposed topology is optimized for different goals. The proposed cascaded structure is compared with other similar topologies. For verifying the performance of the proposed basic symmetric and cascaded structure, results from a computer-based MATLAB/Simulink simulation and from experimental hardware are also discussed.

• Journal of Electrical Engineering and Technology
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• v.11 no.6
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• pp.1674-1683
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• 2016

In this paper, a Finite Control Set Model Predictive Control (FCS-MPC) for a five level cascaded multilevel inverter (CMLI) with reduced switch topology is proposed. Five switches are used here instead of conventionally used eight switches. The main contribution of this paper is to make the MPC controller work for the reduced switch topology using only 19 voltage vectors in place of conventional 61 voltage vectors for a five level CMLI. This simplifies the execution of the MPC algorithm, paving a way for the significant reduction in the computational time. The controller makes use of the excellent ability of MPC to multitask, by adding one more objective which is to reduce the average switching frequency in addition to controlling the load current. This is especially important, since switching losses and therefore switching frequency is significant for high-power applications. The trade-off of this MPC is that the current is not as smooth as the 61 vector scheme, but well within the limits of IEEE standards. The results shown prove that this MPC works well in steady state and dynamic conditions too.

• Journal of Electrical Engineering and Technology
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• v.13 no.2
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• pp.688-698
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• 2018

Quasi Z-Source Multilevel Inverter (QZMLI) topology has attracted grid connected Photovoltaic (PV) systems in recent days. So there is a remarkable research thrust in switching techniques and control strategies of QZMLI. This paper presents the mathematical analysis of Phase shift- Pulse Width Amplitude Modulation (PS-PWAM) for QZMLI and emphasizes on the advantages of the technique. The proposed technique uses the maximum and minimum envelopes of the reference waves for generation of pulses and proportion of it to generate shoot-through pulses. Hence, it results in maximum utilization of input voltage, lesser switching loss, reduced Total Harmonic Distortion (THD) of the output voltage, reduced inductor current ripple and capacitor voltage ripple. Due to these qualities, the QZMLI with PS-PWAM emerges to be the best suitable for PV based grid connected applications compared to Phase shift-Pulse Width Modulation (PS-PWM). The detailed math analysis of the proposed technique has been disclosed. Simulation has been performed for the proposed technique using MATLAB/Simulink. A prototype has been built to validate the results for which the pulses were generated using FPGA /SPARTAN 3E.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.13 no.3
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• pp.25-33
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• 1999

In this paper, the method of reducing hanmnics and correcting of power factor in single PWM converter associated with diode rectifier and boost converter is studied. In the general diode rectifier there are sorre problems that discontinuous current of reducing power factor and including distortion of hanmnics at the input current affects other sources. To solve the problems of performance degradation due to pulse wavefonn in the input current, the ac-dc converter in which the hanmnic distortion in the input current is reduced using a third-hanmnic-injected PWM is proposed. A lower power loss of switching and easy configuration of circuit are obtained by adopting discontinuous current mode. Simulation and experimental results of ac-dc converter with 5[kHz] switching frequency are presented and correction of power factor and reduction of total hanmnic distortion was established.lished.

• Journal of Biomedical Engineering Research
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• v.25 no.4
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• pp.269-275
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• 2004

Different biological tissues have different values of electrical resistivity. In EIT (electrical impedance tomography), we try to provide cross-sectional images of a resistivity distribution inside an electrically conducting subject such as the human body mainly for functional imaging. However, it is well known that the image reconstruction problem in EIT is ill-posed and the quality of a reconstructed image highly depends on the measurement error. This requires us to develop a high-performance EIT system. In this paper, we describe the development of a 16-channel digital EIT system including a single constant current source, 16 voltmeters, main controller, and PC. The system was designed and implemented using the FPGA-based digital technology. The current source injects 50KHz sinusoidal current with the THD (total harmonic distortion) of 0.0029% and amplitude stability of 0.022%. The single current source and switching circuit reduce the measurement error associated with imperfect matching of multiple current sources at the expense of a reduced data acquisition time. The digital voltmeter measuring the induced boundary voltage consists of a differential amplifier, ADC, and FPGA (field programmable gate array). The digital phase-sensitive demodulation technique was implemented in the voltmeter to maximize the SNR (signal-to-noise ratio). Experimental results of 16-channel digital voltmeters showed the SNR of 90dB. We used the developed EIT system to reconstruct resistivity images of a saline phantom containing banana objects. Based on the results, we suggest future improvements for a 64-channel muff-frequency EIT system for three-dimensional dynamic imaging of bio-impedance distributions inside the human body.

• Journal of Power Electronics
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• v.15 no.3
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• pp.670-684
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• 2015

The hybrid cascaded multilevel inverter (HCMLI) is a popular converter topology that is being increasingly used in high power medium voltage drives. The intricacy of the control technique for a HCMLI increases with the number of levels and due to fluctuating dc voltages. This paper presents a novel offline quadrant search based space vector modulation technique to synthesize a sinusoidal output from a dispersed pattern of voltage vectors due to different voltages in the auxiliary unit. Such an investigation has never been reported in the literature and it is being attempted for the first time. The method suggested distributes the voltage vectors for a reduced total harmonic distortion at minimal computation. In addition, the proposed algorithm determines the maximum modulation index in the linear modulation range in order to synthesize a sinusoidal output for both normal and abnormal vector patterns. It is better suited for a wide range of practical applications. It is particularly well suited for renewable source fed inverters which utilize large capacitor banks to maintain the dc link, which are prone to such slow fluctuations. The proposed quadrant search space vector modulation technique is simulated using MATLAB/SIMULINK and implemented using a Nexys-2 Spartan-3E FPGA for a developed prototype.