• Journal of KIISE:Computer Systems and Theory
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• v.34 no.10
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• pp.467-473
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• 2007

Power-aware design is one of the most important areas to be emphasized in multimedia mobile systems, in which data transfers dominate the power consumption. In this paper, we propose a new architecture for motion compensation (MC) of H.264/AVC with power reduction by decreasing the data transfers. For this purpose, a reconfigurable microarchitecture based on data type is proposed for interpolation and it is mapped onto the dedicated motion compensation IP (intellectual property) effectively without sacrificing the performance or the system latency. The original quarter-pel interpolation equation that consists of one or two half-pel interpolations and one averaging operation is designed to have different execution control modes, which result in decreasing memory accesses greatly and maintaining the system efficiency. The simulation result shows that the proposed method could reduce up to 87% of power consumption caused by data transfers over the conventional method in MC module.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.45 no.9
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• pp.711-723
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• 2017

This paper proposes a flight control system for an organic flight array(OFA) which has a new configuration to consist of multi modularized ducted-fan unmanned aerial vehicles (UAVs). The OFA is able to apply to various missions such as indoor reconnaissance, communication relay, and radar jamming by using capability of hover flight. The OFA has a distinguished advantage due to reconfigurable structure to assemble or separate with respect to its missions or operational conditions. A dynamic modelling of the OFA is derived based on equations of motion of the single ducted-fan modules. In order to apply nonlinear control method, an affine system of attitude dynamics is derived. Moreover, the control system is composed of a back-stepping controller for attitude control and a PID controller for position control. Then the performance of the proposed controller is verified via a numerical simulation under wind disturbance.

• The KIPS Transactions:PartA
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• v.12A no.5 s.95
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• pp.451-460
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• 2005

We present a methodology to design energy-efficient data paths using FPGAs. Our methodology integrates domain specific modeling, coarse-grained performance evaluation, design space exploration, and low-level simulation to understand the tradeoffs between energy, latency, and area. The domain specific modeling technique defines a high-level model by identifying various components and parameters specific to a domain that affect the system-wide energy dissipation. A domain is a family of architectures and corresponding algorithms for a given application kernel. The high-level model also consists of functions for estimating energy, latency, and area that facilitate tradeoff analysis. Design space exploration(DSE) analyzes the design space defined by the domain and selects a set of designs. Low-level simulations are used for accurate performance estimation for the designs selected by the DSE and also for final design selection We illustrate our methodology using a family of architectures and algorithms for matrix multiplication. The designs identified by our methodology demonstrate tradeoffs among energy, latency, and area. We compare our designs with a vendor specified matrix multiplication kernel to demonstrate the effectiveness of our methodology. To illustrate the effectiveness of our methodology, we used average power density(E/AT), energy/(area x latency), as themetric for comparison. For various problem sizes, designs obtained using our methodology are on average $25\%$ superior with respect to the E/AT performance metric, compared with the state-of-the-art designs by Xilinx. We also discuss the implementation of our methodology using the MILAN framework.

• Journal of Broadcast Engineering
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• v.21 no.5
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• pp.803-815
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• 2016

In this paper, we design a direct radio frequency (RF) sampling receiver for multiband GNSS signals and demonstrate its performance. The direct RF sampling is a technique that does not use an analog mixer, but samples the passband signal directly, and all receiver processes are done in digital domain, whereas the conventional intermediate frequency (IF) receiver samples the IF band signals. In contrast to the IF sampling receiver, the RF sampling receiver is less complex in hardware, reconfigurable, and simultaneously converts multiband signals to digital signals with an analog-to-digital (AD) converter. The reconfigurability and simultaneous reception are very important in military applications where rapid change to other system is needed when a system is jammed by an enemy. For simultaneous reception of multiband signals, the sampling frequency should be selected with caution by considering the carrier frequencies, bandwidths, desired intermediate frequencies, and guard bands. In this paper, we select a sampling frequency and design a direct RF sampling receiver to receive multiband global navigation satellite system (GNSS) signals such as GPS L1, GLONASS G1 and G2 signals. The receiver is implemented with a commercial AD converter and software. The receiver performance is demonstrated by receiving the real signals.

• Journal of the Korean Institute of Intelligent Systems
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• v.8 no.5
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• pp.83-97
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• 1998

This paper developes an integrated environment CAD system that can design and implement an accurate and cost-effective FLC automatically. For doing this, an integrated development environment (IDE) (called FADIS; FLC Automatic Design and Implementation Station) is built by the seemless coupling of many existing. CAD tools in an attempt to the FADIS performs various functions such that (1) i~utomatically generate the VHDL components appropriate for the proposed FLC architecture from the various design parameters (2) simulate the generated VHDL code on the Synopsys's VHDL Simulator, (3) automatically compiler, (4) generate the optimized, placed, and routed rawbit files from the synthesized modules by Xilinx's XactStep 6.0, (5) translate the rawbit files into the downloadable ex- [:cution reconfigurable FPGA board (VCC's EVCI), and (7) continuously monitor the control status graphically by communicating the FLC with the controlled target via S-bus. The developed FADIS is tested for its validity by carrying out the overall procedures of designing and implementing the FLC required for the truck-backer upper control, the reduction of control execution time due to the controller's FPGA implementation is verified by comparing with other implementations.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.1
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• pp.76-84
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• 2009

This paper proposes a SOC platform which is eligible for education and application SOC design. The platform, fully synthesizable and reconfigurable, includes the OpenRISC embedded processor, some basic peripherals such as GPIO, UART, debug interlace, VGA controller and WISHBONE interconnect. The platform uses a set of development environment such as compiler, assembler, debugger and RTOS that is built for HW/SW system debugging and software development. Designed SOC, IPs and Testbenches are described in the Verilog HDL and verified using commercial logic simulator, GNU SW development tool kits and the FPGA. Finally, a multimedia SOC derived from the SOC platform is implemented to ASIC using the Magnachip cell library based on 0.18um 1-poly 6-metal technology.

• Journal of the Korea Institute of Military Science and Technology
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• v.26 no.1
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• pp.91-101
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• 2023

Modeling and Simulation(M&S) technology has been widely used to solve constraints such as time, space, safety, and cost when we implement the same development and test environments as real warfare environments to develop, test, and evaluate weapon systems for the last several decades. The integration and test environments employed for development and test & evaluation are required to provide Live Virtual Construction(LVC) simulation environments for carrying out requirement analysis, design, integration, test and verification. Additionally, they are needed to provide computing environments which are possible to reconfigure computing resources and software components easily according to test configuration changes, and to run legacy software components independently on specific hardware and software environments. In this paper, an Integration Test and Simulation for Engagement Control(ITSEC) bed using a bare-metal virtualization mechanism is proposed to meet the above test and simulation requirements, and it is applied and implemented for an air missile defense system. The engagement simulation experiment results conducted on air and missile defense environments demonstrate that the proposed bed is a sufficiently cost-effective and feasible solution to reconfigure and expand application software and computing resources in accordance with various integration and test environments.

• Proceedings of the Korea Information Processing Society Conference
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• 2011.04a
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• pp.113-116
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• 2011

최근 IT 기술의 급격한 발전으로 개인정보, 환경 등 다양한 정보를 수시로 수집 및 관리하면서 사용자가 원할시 즉각적인 정보서비스를 제공하고 있다. 그러나 유 무선상의 데이터 전송은 정보의 도청, 메시지의 위 변조 및 재사용, DoS(Denial of Service)등 외부의 공격으로부터 쉽게 노출된다. 이러한 외부 공격은 개인 프라이버시를 포함한 정보서비스 시스템 전반에 치명적인 손실을 야기 시킬 수 있기 때문에 정보보호 시스템의 필요성은 갈수록 그 중요성이 부각되고 있다. 현재까지 정보보호 시스템은 소프트웨어(S/W), 하드웨어(ASIC), FPGA(Field Progr- ammable Array) 디바이스를 이용하여 구현되었으며, 각각의 구현방법은 여러 가지 문제점이 있으며 그에 따른 해결방법이 제시되고 있다. 본 논문에서는 다양한 환경에서의 정보보호 서비스를 제공하기 위한 재구성형 SoC 구조를 제안한다. 제안된 SoC는 비밀키 암호알고리즘(AES), 암호학적 해쉬(SHA-256), 공개키 암호알고리즘(ECC)을 수행 할 수 있으며, 마스터 콘트롤러에 의해 제어된다. 또한 정보보호 시스템이 요구하는 다양한 제약조건(속도, 면적, 안전성, 유연성)을 만족하기 위해 S/W, ASIC, FPGA 디바이스의 모든 장점을 최대한 활용하였으며, MCU와의 효율적인 통신을 위한 I/O 인터페이스를 제안한다. 따라서 제안된 정보보호 시스템은 기존의 시스템보다 다양한 정보보호 알고리즘을 지원할 뿐만 아니라 속도 및 면적에 있어 상충 관계를 개선하였기 때문에 저비용 응용뿐만 아니라 고속 통신 장비 시스템에도 적용이 가능하다.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.18 no.1
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• pp.21-31
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• 2017

In this paper, the Zynq system-on-chip (SoC) platform is used to design an adaptive noise reduction and edge-detection system using partial reconfiguration. Filters are implemented in a partially reconfigurable (PR) region to provide high computational complexity in real-time, 1080p video processing. In addition, partial reconfiguration enables better utilization of hardware resources in the embedded system from autonomous replacement of filters in the same PR region. The proposed edge-detection system performs adaptive noise reduction if the noise density level in the incoming video sequences exceeds a given threshold value. Results of implementation show that the proposed system improves the accuracy of edge-detection results (14~20 times in Pratt's Figure of Merit) through self-reconfiguration of filter bitstreams triggered by noise density level in the video sequences. In addition, the ZyCAP controller implemented in this paper enables about 2.1 times faster reconfiguration when compared to a PCAP controller.

• Proceedings of the Korean Institute of Intelligent Systems Conference
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• 1993.06a
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• pp.975-976
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• 1993

This talk presents the overview of the author's research and development activities on fuzzy inference hardware. We involved it with two distinct approaches. The first approach is to use application specific integrated circuits (ASIC) technology. The fuzzy inference method is directly implemented in silicon. The second approach, which is in its preliminary stage, is to use more conventional microprocessor architecture. Here, we use a quantitative technique used by designer of reduced instruction set computer (RISC) to modify an architecture of a microprocessor. In the ASIC approach, we implemented the most widely used fuzzy inference mechanism directly on silicon. The mechanism is beaded on a max-min compositional rule of inference, and Mandami's method of fuzzy implication. The two VLSI fuzzy inference chips are designed, fabricated, and fully tested. Both used a full-custom CMOS technology. The second and more claborate chip was designed at the University of North Carolina(U C) in cooperation with MCNC. Both VLSI chips had muliple datapaths for rule digital fuzzy inference chips had multiple datapaths for rule evaluation, and they executed multiple fuzzy if-then rules in parallel. The AT & T chip is the first digital fuzzy inference chip in the world. It ran with a 20 MHz clock cycle and achieved an approximately 80.000 Fuzzy Logical inferences Per Second (FLIPS). It stored and executed 16 fuzzy if-then rules. Since it was designed as a proof of concept prototype chip, it had minimal amount of peripheral logic for system integration. UNC/MCNC chip consists of 688,131 transistors of which 476,160 are used for RAM memory. It ran with a 10 MHz clock cycle. The chip has a 3-staged pipeline and initiates a computation of new inference every 64 cycle. This chip achieved an approximately 160,000 FLIPS. The new architecture have the following important improvements from the AT & T chip: Programmable rule set memory (RAM). On-chip fuzzification operation by a table lookup method. On-chip defuzzification operation by a centroid method. Reconfigurable architecture for processing two rule formats. RAM/datapath redundancy for higher yield It can store and execute 51 if-then rule of the following format: IF A and B and C and D Then Do E, and Then Do F. With this format, the chip takes four inputs and produces two outputs. By software reconfiguration, it can store and execute 102 if-then rules of the following simpler format using the same datapath: IF A and B Then Do E. With this format the chip takes two inputs and produces one outputs. We have built two VME-bus board systems based on this chip for Oak Ridge National Laboratory (ORNL). The board is now installed in a robot at ORNL. Researchers uses this board for experiment in autonomous robot navigation. The Fuzzy Logic system board places the Fuzzy chip into a VMEbus environment. High level C language functions hide the operational details of the board from the applications programme . The programmer treats rule memories and fuzzification function memories as local structures passed as parameters to the C functions. ASIC fuzzy inference hardware is extremely fast, but they are limited in generality. Many aspects of the design are limited or fixed. We have proposed to designing a are limited or fixed. We have proposed to designing a fuzzy information processor as an application specific processor using a quantitative approach. The quantitative approach was developed by RISC designers. In effect, we are interested in evaluating the effectiveness of a specialized RISC processor for fuzzy information processing. As the first step, we measured the possible speed-up of a fuzzy inference program based on if-then rules by an introduction of specialized instructions, i.e., min and max instructions. The minimum and maximum operations are heavily used in fuzzy logic applications as fuzzy intersection and union. We performed measurements using a MIPS R3000 as a base micropro essor. The initial result is encouraging. We can achieve as high as a 2.5 increase in inference speed if the R3000 had min and max instructions. Also, they are useful for speeding up other fuzzy operations such as bounded product and bounded sum. The embedded processor's main task is to control some device or process. It usually runs a single or a embedded processer to create an embedded processor for fuzzy control is very effective. Table I shows the measured speed of the inference by a MIPS R3000 microprocessor, a fictitious MIPS R3000 microprocessor with min and max instructions, and a UNC/MCNC ASIC fuzzy inference chip. The software that used on microprocessors is a simulator of the ASIC chip. The first row is the computation time in seconds of 6000 inferences using 51 rules where each fuzzy set is represented by an array of 64 elements. The second row is the time required to perform a single inference. The last row is the fuzzy logical inferences per second (FLIPS) measured for ach device. There is a large gap in run time between the ASIC and software approaches even if we resort to a specialized fuzzy microprocessor. As for design time and cost, these two approaches represent two extremes. An ASIC approach is extremely expensive. It is, therefore, an important research topic to design a specialized computing architecture for fuzzy applications that falls between these two extremes both in run time and design time/cost. TABLEI INFERENCE TIME BY 51 RULES {{{{Time }}{{MIPS R3000 }}{{ASIC }}{{Regular }}{{With min/mix }}{{6000 inference 1 inference FLIPS }}{{125s 20.8ms 48 }}{{49s 8.2ms 122 }}{{0.0038s 6.4㎲ 156,250 }} }}