• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.8
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• pp.619-630
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• 2003

We present a method of runtime configuration scheduling in reconfigurable SoC design. As a model of computation, we use a popular formal model of computation, hierarchical FSM (HFSM) with synchronous dataflow (SDF) model, in short, HFSM-SDF model. In reconfigurable SoC design with HFSM-SDF model, the problem of configuration scheduling becomes challenging due to the dynamic behavior of the system such as concurrent execution of state transitions (by AND relation), complex control flow (HFSM), and complex schedules of SDF actor firing. This makes it hard to hide configuration latency efficiently with compile-time static configuration scheduling. To resolve the problem, it is necessary to know the exact order of required configurations during runtime and to perform runtime configuration scheduling. To obtain the exact order of configurations, we exploit the inherent property of HFSM-SDF that the execution order of SDF actors can be determined before executing the state transition of top FSM. After obtaining the order information and storing it in the ready configuration queue (ready CQ), we execute the state transition. During the execution, whenever there is FPGA resource available, a new configuration is selected from the ready CQ and fetched by the runtime configuration scheduler. We applied the method to an MPEG4 decoder and IS95 design and obtained up to 21.8% improvement in system runtime with a negligible overhead of memory usage.

• Journal of Korea Society of Digital Industry and Information Management
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• v.12 no.4
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• pp.81-87
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• 2016

Recently, as the heterogeneous network (HetNet) has been deployed widely to support various kinds of Radio Access Networks(RANs) with a combination of Macro, Pico, and/or Femto cells, research and standardization efforts have been very active regarding the concept of Licensed Shared Access (LSA) for supporting spectrum sharing. In order for a mobile device to efficiently support the spectrum sharing, the mobile device shall be reconfigurable, meaning that its radio application code has to be adaptively changed in accordance with the hopping of desired spectral band. Especially, Working Group 2 (WG2) of Technical Committee (TC) Reconfigurable Radio System (RRS) of European Telecommunications Standards Institute (ETSI) has been a main driving force for developing standard architecture for Multi-mode Mobile Device (MD) that can be applied to the LSA system. In this paper, we introduce the Multi-mode MD architecture for supporting LSA-based spectrum sharing. An implementation of a test-bed of Multi-mode MD is presented in order to verify the feasibility of the standard MD architecture for the purpose of LSA-based spectrum sharing through various experimental tests.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.34 no.7
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• pp.35-44
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• 2006

When control surface failure occurs, it is conventional to correct a current control or to transform to other control. In this paper, instead of adopting a conventional way, a reconfiguration method which compensate the failure with alternative control surface deflection, depending on the level of failure, by using neural network and PCH(Pseudo-Control Hedging). The Conroller is designed of inner-loop(SCAS : Stability Command Augmentation System) with DMI(Dynamic Model Inversion) and outer-loop with Y axis acceleration feedback for a coordinate turn. Additionally, double PCH method was adopted to prevent actuator saturation and input command was generated to compensate for failure. At the end, The feasibility of the method is validated with randomly selected failure scenarios.

• International Journal of Aeronautical and Space Sciences
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• v.4 no.1
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• pp.1-8
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• 2003

In this paper, a reconfigurable flight control system is designed by applying the sliding mode control scheme. The sliding mode control method is a nonlinear control method which has been widely used because of its merits such as robustness and flexibility. In the sliding mode controller design, the signum function is usually included, but it causes the undesirable chattering problem. The chattering phenomenon can be avoided by using the saturation function instead of signum function. However, the boundary layer of the sliding surface should be carefully treated because of the use of the saturation function. In contrast to the conventional approaches, the thickness of the boundary layer of our approach does not need to be small. The reachability to the boundary layer is guaranteed by the sliding mode controller. The fault detection and isolation process is operated based on a sliding mode observer. To evaluate the reconfiguration performance, a numerical simulation using six degree-of-freedom aircraft dynamics is performed.

• ETRI Journal
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• v.33 no.3
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• pp.326-334
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• 2011

This paper outlines the time jitter effect of a sampling clock on a software-defined radio technology-based digital intermediate frequency (IF) transceiver for a mobile communication base station. The implemented digital IF transceiver is reconfigurable to high-speed data packet access (HSDPA) and three bandwidth profiles: 1.75 MHz, 3.5 MHz, and 7 MHz, each incorporating the IEEE 802.16d worldwide interoperability for microwave access (WiMAX) standard. This paper examines the relationship between the signal-to-noise ratio (SNR) characteristics of a digital IF transceiver with an under-sampling scheme and the sampling jitter effect on a multichannel orthogonal frequency-division multiplexing (OFDM) signal. The simulation and experimental results show that the SNR of the OFDM system with narrower band profiles is more susceptible to sampling clock jitter than systems with relatively wider band profiles. Further, for systems with a comparable bandwidth, HSDPA outperforms WiMAX, for example, a 5 dB error vector magnitude improvement at 15 picoseconds time jitter for a bandwidth of WiMAX 3.5 MHz profile.

• 전자공학회논문지 IE
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• v.46 no.2
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• pp.7-10
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• 2009

This paper presents the implementation of libraries of hardware modules for genetic algorithm using VHDL. Evolvable hardware refers to hardware that can change its architecture and behavior dynamically and autonomously by interacting with its environment. So, it is especially suited to applications where no hardware specifications can be given in advance. Evolvable hardware is based on the idea of combining reconfigurable hardware device with evolutionary computation, such as genetic algorithm. Because of parallel, no function call overhead and pipelining, a hardware genetic algorithm give speedup over a software genetic algorithm. This paper suggests the hardware genetic algorithm for evolvable embedded system chip. That includes simulation results and analysis for several fitness functions. It can be seen that our design works well for the three examples.

• The KIPS Transactions:PartA
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• v.9A no.4
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• pp.459-466
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• 2002

Modern embedded system employs a hybrid architecture which contains a general micro processor and reconfigurable devices such as FPGAS to retain flexibility and to meet timing constraints. It is a hard and important problem for embedded system designers to explore and find a right system configuration, which is known as design space exploration (DSE). With DES, it is possible to predict a final system configuration during the design phase before physical implementation. In this paper, we implement a timing analysis simulator for a DSE on a hybrid embedded system. The simulator, integrating exiting timing analysis tools for hardware and software, is designed by extending Y-chart approach, which allows quantitative performance analysis by varying design parameters. This timing analysis simulator is expected to reduce design time and costs and be used as a core module of a DSE for a hybrid embedded system.

• Journal of Korea Multimedia Society
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• v.17 no.3
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• pp.324-332
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• 2014

This paper presents a programmable System-On-a-chip for various embedded applications that need Neural Network computations. The system is fully implemented into Field-Programmable Gate Array (FPGA) based prototyping platform. The SoC consists of an embedded processor core and a reconfigurable hardware accelerator for neural computations. The performance of the SoC is evaluated using real image processing applications, such as optical character recognition (OCR) system.

• Journal of Korea Multimedia Society
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• v.10 no.1
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• pp.66-73
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• 2007

SDR technology is a fundamental wireless access technology that combines and accommodates multiple wireless communication standards in one transceiver system through just modifying software using modular communication platforms without any hardware modifications for RF and IF signal processing on the basis of high performance DSP devices. Various communication systems that are designed under diverse and complex network environments require the communication platforms on the basis of SDR supporting reorganization to guarantee simple and fast communication interfaces among the respective wireless networks. This paper introduces a main idea on the implementation of platform on the basis of SDR and a communication platform is designed for experiments that is composed of a DSP board with TMS320C6713 CPU, a FPGA board processing IF signals, and a module with RF transceiver processing wireless LAN frequency bandwidth. Various modulation schemes(BPSK, QPSK, and 16QAM) used in communication systems are applied and tested on the designed platform and the test results shows that it is possible to design a reconfigurable communication terminal platform.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.26 no.5
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• pp.521-524
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• 2015

This letter presents a selective wireless power transfer architecture using a reconfigurable multi-port amplifier. The proposed wireless power transfer architecture is composed of a phase shifter part controlled by FPGA, two class-E power amplifiers, a four-port power combiner and two coil loads. Depending on the phase control of FPGA, the power ratio of outputs at the two coil loads becomes 1:1, 2:0 and 0:2. The manufactured system has delivered 1W DC power to loads at 125 kHz. The total DC-to-DC conversion efficiency shows more than 40 % including PA efficiency of 79 %.