• JSTS:Journal of Semiconductor Technology and Science
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• v.9 no.4
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• pp.209-215
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• 2009

Reconfigurable array architecture is recently attracting much attention. It is a flexible hardware architecture, which can dynamically change its configuration to execute various functions while maintainning high performance. However, pursuing flexibility and performance at the same time leads to complexity, thereby makes the mapping of applications a difficult process. There have been attempts to use compiler or high level synthesis techniques to solve the problem. In this paper, we propose yet another method, which uses libraries for the mapping to provide an abstracttion of the internal structure and at the same time to reduce the development time and efforts through the automated process. We have selected a JPEG decoder as an example to apply the proposed method. As a result, we obtained about 20% less performance compared to manual mapping but development time is dramatically reduced to less than 1%.

• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.1
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• pp.145-149
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• 2015

A reconfigurable lighting engine for widely used lighting models is proposed for low-power GPU shaders. Conventionally, lighting operations that involve many complex arithmetic operations were calculated by the shader programs on the GPU, which led to a significant energy overhead. In this letter, we propose a lighting engine to improve the energy-efficiency by supporting the widely used advanced lighting models in hardware. It supports the Blinn-Phong, Oren-Nayar, and Cook-Torrance models, by exploiting the logarithmic arithmetic and optimizing the trigonometric function evaluations for the energy-efficiency. Experimental results demonstrate 12.7%, 42.5%, and 35.5% reductions in terms of power-delay product from the shader program implementations for each lighting model. Moreover, our work shows 10.1% higher energy-efficiency for the Blinn-Phong model compared to the prior art.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.57 no.9
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• pp.1652-1659
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• 2008

With the increase of huge amount of data in network systems, ultimate high-speed network has become an essential requirement. In such systems, the encryption and decryption process for security becomes a bottle-neck. For this reason, the need of hardware implementation is strongly emphasized. In this study, a mixed inner and outer round pipelining architecture is introduced to achieve high speed performance of ARIA hardware. Multiplexers are used to control the lengths of rounds for 3 types of keys. Merging of encryption module and key initialization module increases the area efficiency. The proposed hardware architecture is implemented on reconfigurable hardware, Xilinx Virtex2-pro. The hardware architecture in this study shows that the area occupied 6437 slices and 128 BRAMs, and it is translated to throughput of 24.6Gbit/s with a maximum clock frequency of 192.9MHz.

• Proceedings of the IEEK Conference
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• 2007.07a
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• pp.449-450
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• 2007

Evolvable hardware(EHW) is a dynamic field that brings together reconfigurable hardware, artificial intelligence, fault tolerance and autonomous systems. This paper gives an introduction to the field. The features that can be used to identify and classify evolvable hardware are the evolutionary algorithm, the implementation and the genotype representation. Evolvable hardware (EHW) is hardware that can change its own circuit structure by genetic learning to achieve maximum adaptation to the environment. In conventional EHW, the learning is executed by software on a computer.

• Journal of KIISE:Software and Applications
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• v.32 no.1
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• pp.62-73
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• 2005

Evolvable Hardware is the technique that obtains target function by adapting reconfigurable digital' devices to environment in real time using evolutionary computation. It opens the possibility of automatic design of hardware circuits but still has the limitation to produce complex circuits. In this paper, we have analyzed the fitness landscape of evolvable hardware and proposed a speciation technique of evolving diverse individuals simultaneously, proving the efficiency empirically. Also, we show that useful extra functions can be obtained by analyzing diverse circuits from the speciation technique.

• Journal of the Korean Institute of Intelligent Systems
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• v.11 no.5
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• pp.426-432
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• 2001

This paper is implementation of cellular automata neural network system using evolving hardware concept. This system is a living creatures'brain based on artificial life techniques. Cellular automata neural network system is based on the development and the evolution, in other words, it is modeled on the ontogeny and phylogney of natural living things. The phylogenetic mechanism are fundamentally non-deterministic, with the mutation and recombination rate providing a major source of diversity. Ontogeny is deterministic and local physics. Cellular automata is developed from initial cells, and evaluated in given environment. And genetic algorithms take a part in adaptation process. In this paper we implement this system using evolving hardware concept. Evolving hardware is reconfigurable hardware whose configuration si under the control of an evolutionary algorithm. We design genetic algorithm process for evolutionary algorithm and cells in cellular automata neural network for the construction of reconfigurable system. The effectiveness of the proposed system if verified by applying it to Exclusive-OR.

• Proceedings of the KIEE Conference
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• 2006.10d
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• pp.166-168
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• 2006

This paper presents a speed control of AC servo system using LabVIEW program and cRIO (Compact RIO)hardware which is a real-time controller made in National Instruments company. LabVIEW is a GUI programming language easy to implement control system and cRIO is a reconfigurable hardware platform which is very simple. Therefore Lab VIEW and cRIO will be excellent tools to design and implement control system.

• Journal of Korea Multimedia Society
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• v.17 no.3
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• pp.324-332
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• 2014

This paper presents a programmable System-On-a-chip for various embedded applications that need Neural Network computations. The system is fully implemented into Field-Programmable Gate Array (FPGA) based prototyping platform. The SoC consists of an embedded processor core and a reconfigurable hardware accelerator for neural computations. The performance of the SoC is evaluated using real image processing applications, such as optical character recognition (OCR) system.

• Proceedings of the Korean Institute of Communication Sciences Conference
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• 2004.11a
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• pp.426-426
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• 2004

• Journal of Korea Multimedia Society
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• v.12 no.5
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• pp.617-632
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• 2009

In this paper we propose a technique of implementing the reconfigurable network protocol stack that allows for partitioning network protocol functions into software and hardware tasks on a SoC (System on Chip) platform. Additionally, we present a method that guarantees the deadline of both an individual task and messages exchanging among tasks in order to meet the deadline of real-time multimedia and networking services. The proposed real-time message exchange method guarantees the deadline of messages generated by multimedia services that are required to meet the real-time properties of multimedia applications. After implementing the networking functions of TCP/IP protocol suite into hardware and software tasks, we verify and validate their performance on the SoC platform. Experimental results indicate that the proposed technique improves the performance of TCP/IP protocol suit as well as application service satisfaction in application-specific real-time.