• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.23 no.7
• /
• pp.791-796
• /
• 2012

A RF limiter is a component to protect the receiver front end from undesired signal. A RF limiter is a key component whose output is constant level for all inputs above a critical value. A RF limiter use a diode to pass signals of low power while attenuating those above some threshold. A RF limiter for receiver protection in modern radar systems is playing a vital role in order to meet challenges of new interference threats and complicated electromagnetic environments. This paper proposed a new circuit for high power RF limiter whose structure is the combination of the PIN diode and Limit diode. PIN diode take a use of its isolation characteristics which act as a switch does. A 2 kW RF limiter with 200 us pulse width at S-band was developed. It shows good agreements between estimated value and measured results.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.17 no.4
• /
• pp.552-560
• /
• 2017

This paper presents a transceiver chipset realized in a $0.13-{\mu}m$ CMOS technology for serial digital interface of video data transmission, which compensates the electrical cable loss of 45 dB in maximum at 1.5 Gbps. For the purpose, the TX equips pre-emphasis in the main driver by utilizing a D-FF with clocks generated from a wide-range tuning PLL. In RX, two-stage continuous-time linear equalizers and a limiting amplifier are exploited as a front-end followed by a 1/8-rate CDR to retime the data with inherent 1:8 demultiplexing function. Measured results demonstrate data recovery from 270 Mbps to 1.5 Gbps. The TX consumes 104 mW from 1.2/3.3-V supplies and occupies the area of $1.485mm^2$, whereas the RX dissipate 133 mW from a 1.2-V supply and occupies the area of $1.44mm^2$.

• Journal of information and communication convergence engineering
• /
• v.13 no.4
• /
• pp.235-240
• /
• 2015

A decimation chain for multi-standard reconfigurable radios is presented for 900-MHz and 1,900-MHz dual-band cellular standards with a data interpolator based on the Lagrange method for adjusting the variable data rate to a fixed data rate appropriate for each standard. The two proposed configurations are analyzed and compared to provide insight into aliasing and the signal bandwidth by means of a newly introduced measure called interpolation error. The average interpolation error is reduced as the ratio of the sampling frequency to the signal BW is increased. The decimation chain and the multi-rate analog-to-digital converter are simulated to compute the interpolation error and the output signal-to-noise ratio. Further, a method to operate the above-mentioned chain under a compressed mode of operation is proposed in order to guarantee continuous packet connectivity for inter-radio-access technologies. The presented decimation chain can be applied to LTE, WCDMA, GSM multi-mode multi-band digital front-end which will ultimately lead to the software-defined radio.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.11 no.4
• /
• pp.295-301
• /
• 2011

A triple-band transceiver module for 2.3/2.5/3.5 GHz mobile WiMAX, IEEE 802.16e, applications is introduced. The suggested transceiver module consists of RFIC, reconfigurable/multi-resonance MIMO antenna, embedded PCB, mobile WiMAX base band, memory and channel selection front-end module. The RFIC is fabricated in $0.13{\mu}m$ RF CMOS process and has 3.5 dB noise figure(NF) of receiver and 1 dBm maximum power of transmitter with 68-pin QFN package, $8{\times}8\;mm^2$ area. The area reduction of transceiver module is achieved by using embedded PCB which decreases area by 9% of the area of transceiver module with normal PCB. The developed triple-band mobile WiMAX transceiver module is tested by performing radio conformance test(RCT) and measuring carrier to interference plus noise ratio (CINR) and received signal strength indication (RSSI) in each 2.3/2.5/3.5 GHz frequency.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.11 no.4
• /
• pp.238-246
• /
• 2011

A 3-5 GHz UWB radar chip in 0.13 ${\mu}m$ CMOS process is presented in this paper. The UWB radar transceiver for surveillance and biometric applications adopts the equivalent time sampling architecture and 4-channel time interleaved samplers to relax the impractical sampling frequency and enhance the overall scanning time. The RF front end (RFFE) includes the wideband LNA and 4-way RF power splitter, and the analog signal processing part consists of the high speed track & hold (T&H) / sample & hold (S&H) and integrator. The interleaved timing clocks are generated using a delay locked loop. The UWB transmitter employs the digitally synthesized topology. The measured NF of RFFE is 9.5 dB in 3-5 GHz. And DLL timing resolution is 50 ps. The measured spectrum of UWB transmitter shows the center frequency within 3-5 GHz satisfying the FCC spectrum mask. The power consumption of receiver and transmitter are 106.5 mW and 57 mW at 1.5 V supply, respectively.

• The Journal of the Korea institute of electronic communication sciences
• /
• v.7 no.6
• /
• pp.1449-1454
• /
• 2012

Received signal strength indicator (RSSI) represents the strength of the received signal at the front end of analog-to-digital convertor (ADC) input. RSSI value can be used for deciding the status of channel at the receiver. In this paper, the usage of RSSI in handover is studied using the practical measurement data. We first measure RSSI in 5.9GHz frequency band which is commonly used in wireless access in vehicular environments (WAVE) system. i.e., vehicular communications. Then, to implement a fast handover, the usability of RSSI data is analyzed based on the measured data. We also apply handover in practical highway environments.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.15 no.3
• /
• pp.381-389
• /
• 2015

A fully integrated multistandard multiband CMOS mobile TV tuner with small silicon area and low power consumption is proposed for receiving multiple mobile digital TV signals and FM signal. In order to reduce the silicon area of the multistandard multiband receiver, other RF front-end circuits except LNAs are shared and a local oscillator (LO) signal generation architecture with a single VCO for a frequency synthesizer is proposed. To reduce the low frequency noise and the power consumption, a vertical NPN BJT is used in an analog baseband circuits. The RF tuner IC is implemented in a $0.18-{\mu}m$ CMOS technology. The RF tuner IC satisfies all specifications for DVB-H/T, T-DMB, and ISDB-T with a sufficient margin and a successful demonstration has been carried out for DVB-H/T, T-DMB, and ISDB-T with a digital demodulator.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.40 no.8
• /
• pp.549-554
• /
• 2003

In this paper, we have designed and implemented by a monolithic microwave integrated circuit(MMIC) of a 5.8GHz-band low noise amplifier (LNA) composed of receiver front-end(RFE) in a on-board equipment system for dedicated short range communication. The designed LNA is provided with two active devices, matching circuits, and two drain bias circuits. Operating at a single supply of 3V and a consumption current of 18mA, The gain at center frequency 5.8GHz is 13.4dB, NF is 1.94dB, Input IP3 is -3dBm, S$_{11}$ is -18dB, and S$_{22}$ is -13.3dB. The circuit size is 1.2 $\times$ 0.7 $\textrm{mm}^2$.>.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.22 no.1
• /
• pp.91-99
• /
• 2018

This paper has proposed a low-noise and high-linear RF receiver supporting TV white space from 470 MHz to 698 MHz), which is implemented in $0.13-{\mu}m$ CMOS technology. It consists of a low-noise amplifier, a RF band-pass filter, a RF amplifier, a passive down-conversion mixer, and a channel-selection low-pass filter. A low-noise amplifier and RF amplifier provide a high voltage gain to improve the sensitivity level. To suppress strong and nearby interferers, two RF filtering schemes have been performed by using a RF BPF and a down-conversion mixer. The proposed LPF has been based on the common-gate topology and adopted a bi-quad cell to achieve -24dB/oct characteristics. In addition, the RF receiver can support the overall TV band by controlling a LO frequency. The simulated results show a voltage gain of 56 dB, a noise figure of less than 2 dB, and an out-of-channel IIP3 of -2.3 dBm. It consumes 37 mA from a 1.5 V supply voltage.

• ETRI Journal
• /
• v.26 no.3
• /
• pp.229-240
• /
• 2004

This paper reports on our development of a dual-mode transceiver for a CMOS high-rate Bluetooth system-onchip solution. The transceiver includes most of the radio building blocks such as an active complex filter, a Gaussian frequency shift keying (GFSK) demodulator, a variable gain amplifier (VGA), a dc offset cancellation circuit, a quadrature local oscillator (LO) generator, and an RF front-end. It is designed for both the normal-rate Bluetooth with an instantaneous bit rate of 1 Mb/s and the high-rate Bluetooth of up to 12 Mb/s. The receiver employs a dualconversion combined with a baseband dual-path architecture for resolving many problems such as flicker noise, dc offset, and power consumption of the dual-mode system. The transceiver requires none of the external image-rejection and intermediate frequency (IF) channel filters by using an LO of 1.6 GHz and the fifth order onchip filters. The chip is fabricated on a $6.5-mm^{2}$ die using a standard $0.25-{\mu}m$ CMOS technology. Experimental results show an in-band image-rejection ratio of 40 dB, an IIP3 of -5 dBm, and a sensitivity of -77 dBm for the Bluetooth mode when the losses from the external components are compensated. It consumes 42 mA in receive ${\pi}/4-diffrential$ quadrature phase-shift keying $({\pi}/4-DQPSK)$ mode of 8 Mb/s, 35 mA in receive GFSK mode of 1 Mb/s, and 32 mA in transmit mode from a 2.5-V supply. These results indicate that the architecture and circuits are adaptable to the implementation of a low-cost, multi-mode, high-speed wireless personal area network.