• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• v.9 no.2
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• pp.481-484
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• 2005

The direct conversion method is classified into the structure using the mixing technology and six-port scheme. In the view point of complexity and integration the direct conversion method using the six-port scheme is superior to that with mixing technology. Expecially, the six-port direct conversion technology provides the low power consumption and the broad-band characteristic. In this paper, the six-port direct conversion receiver with the branch-line coupler and the ring hybrid coupler is designed respectively. The performances of the designed six-port schemes are analyzed and the six-port scheme with superior performance characteristics is proposed.

• Proceedings of the IEEK Conference
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• 2000.11a
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• pp.333-336
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• 2000

This paper describes a CMOS low noise amplifier (LNA) with bias current reusing architecture intended lot use in the front-end of IMT-2000 receiver. It has been implemented in a 0.35$\mu\textrm{m}$ CMOS process with two poly and four metal layers. In order to accuracy of simulation, we considered a bonding wire and a pad effect and used the measurements of capacitors and on-chip inductors which implemented in the same process. The LNA has a forward gain (S21) of 17 ㏈ and a noise fjgure of 1.26 ㏈. And it has a third-order intermodulation intercept point (IP3) of +3.15 ㏈m and a 1㏈ compression point (P1㏈) of -16 ㏈m, input referred, respectively. The power consumption is 19 ㎽ from a 3V supply.

• JSTS:Journal of Semiconductor Technology and Science
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• v.12 no.4
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• pp.426-432
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• 2012

A fully-integrated low power K-band radar transceiver in 130 nm CMOS process is presented. It consists of a low-noise amplifier (LNA), a down-conversion mixer, a power amplifier (PA), and a frequency synthesizer with injection locked buffer for driving mixer and PA. The receiver front-end provides a conversion gain of 19 dB. The LNA achieves a power gain of 15 dB and noise figure of 5.4 dB, and the PA has an output power of 9 dBm. The phase noise of VCO is -90 dBc/Hz at 1-MHz offset. The total dc power dissipation of the transceiver is 142 mW and the size of the chip is only $1.2{\times}1.4mm^2$.

• Proceedings of the Korean Institute of Communication Sciences Conference
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• 2006.07a
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• pp.416-416
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• 2006

• ETRI Journal
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• v.29 no.5
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• pp.607-613
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• 2007

Most signal-to-noise ratio (SNR) estimation techniques in digital communication channels derive the SNR estimates solely from samples of the received signal after the matched filter. They are based on symbol SNR and assume perfect synchronization and intersymbol interference (ISI)-free symbols. In severe channel distortion where ISI is significant, the performance of these estimators badly deteriorates. We propose an SNR estimator which can operate on data samples collected at the front-end of a receiver or at the input to the decision device. This will relax the restrictions over channel distortions and help extend the application of SNR estimators beyond system monitoring. The proposed estimator uses the characteristics of the second order moments of the additive white Gaussian noise digital communication channel and a linear predictor based on the modified-covariance algorithm in estimating the SNR value. The performance of the proposed technique is investigated and compared with other in-service SNR estimators in digital communication channels. The simulated performance is also compared to the Cram$\acute{e}$r-Rao bound as derived at the input of the decision circuit.

• Journal of Positioning, Navigation, and Timing
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• v.11 no.2
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• pp.127-134
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• 2022

In this paper, a low-cost, flexible GPS simulator based on USRP is designed as a general-purpose software wireless front-end. The simulator consists of a software GPS signal generator and a USRP-based RF transmitter. The simulator supports various scenarios including specified reception time, quantization bit level, I/Q data types, IF frequency, sampling frequency, SNR, ionospheric delay and user dynamics. The generated GPS RF signal is verified using the spectrum analyzer and off-the-shelf GNSS receivers such as U-blox M8T. The experimental results shows that the difference between generated and real live signal is ignorable. It is expected that designed GPS simulator can be used to GNSS signal design, receiver design and signal processing algorithms such as anti-jamming.

• Journal of Satellite, Information and Communications
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• v.5 no.1
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• pp.58-62
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• 2010

This paper presents the effects of RF performance parameters on the Galileo receiver design via simulation after reviewing the requirements of the Galileo receiver structure. At first, we considered the general requirements, structure and characteristics of the Galileo system. Then we designed the Galileo receiver focused on performance requirement of 16 dB C/N which is equal to 15 % Error Vector Magnitude(EVM) by using Advanced Design System(ADS) simulation program. In order to verify the function of Automatic Gain Control(AGC)), we measured the IF output power level by changing the input power level at the front - end of the receiver. We analyzed the performance degradation due to phase noise variations of Local Oscillator(LO) in the Galileo receiver through EVM when the minimum sensitivity level of -127 dBm is applied at the receiver. We also analyzed the performance degradation according to variable Analog-to-Digital Converter(ADC) bits within the Dynamic range, -92 ~ -139 dBm, which has been defined by gain range (-2.5 ~ +42.5 dB) in the AGC operation. The results clearly show that the performance of the Galileo receiver can be improved by increasing ADC bits and reducing Phase Noise of LO.

• Proceedings of the IEEK Conference
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• 2005.11a
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• pp.769-772
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• 2005

This paper describes a low-voltage and low-power channel selection analog front end with continuous-time low pass filters and highly linear programmable-gain amplifier(PGA). The filters were realized as balanced Gm-C biquadratic filters to achieve a low current consumption. High linearity and a constant wide bandwidth are achieved by using a new transconductance(Gm) cell. The PGA has a voltage gain varying from 0 to 65dB, while maintaining a constant bandwidth. A filter tuning circuit that requires an accurate time base but no external components is presented. With a 1-Vrms differential input and output, the filter achieves -85dB THD and a 78dB signal-to-noise ratio. Both the filter and PGA were implemented in a 0.18um 1P6M n-well CMOS process. They consume 3.2mW from a 1.8V power supply and occupy an area of $0.19mm^2$.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.20 no.12
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• pp.1287-1296
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• 2009

It is very important to estimate the Signal to Noise Ratio(SNR) of received signal in time varying channel state. Most SNR estimation techniques derive the SNR estimates solely from the samples of the received signal after the matched filter. In the severe distorted wireless channel, the performance of these estimators become unstable and degraded. LP-based SNR estimator which can operate on data samples collected at the front-end of a receiver shows more stable performance than other SNR estimator. In this paper, we study an efficient SNR estimation algorithm based on LP and propose a new estimation method to decrease the computation complexity. Proposed algorithm accomplishes the SNR estimation process efficiently because it uses the forward prediction error and its conjugate value during the linear prediction error update. Via the computer simulation, the performance of this proposed estimation method is compared and discussed with other conventional SNR estimators in digital communication channels.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.2
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• pp.54-61
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• 1999

This paper describes the design of a 4-Mbps wireless infrared data transceiver chip. The receiver consits of the analog front-end, clock recovery and frame generator, and demodulator. The transmitter consists of the demodulator and LED driver. The versatile analog front- end consisting of multiple amplifiers makes it possible for the chip to be applied to various infrared environments by compensating DC and offset signal components. A 4PPM (pulse position modulation) scheme is used for data transfer in order to meet the IrDA standards. The chip was fabricated in a $0.8-{\mu}m$ 2-poly, 2-metal CMOS technology and dissipates 122mW for ${\pm}2.5V$ supply.