• Journal of Positioning, Navigation, and Timing
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• v.10 no.4
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• pp.307-313
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• 2021

Modernized GNSS signal structures tend to use tiered codes, and all GNSSs use binary codes as secondary codes. However, recently, signals using polyphase codes such as Zadoff-Chu sequence have been proposed, and are expected to be utilized in GNSS. For example, there is Tiered Differential Polyphase Code (TDPC) using polyphase code as secondary code. In TDPC, the phase of secondary code changes every one period of the primary code and a time-variant error is added to the carrier tracking error, so carrier tracking ambiguity exists until the secondary code phase is found. Since the carrier tracking ambiguity cannot be solved using the general GNSS receiver architecture, a new receiver architecture is required. Therefore, in this paper, we describe the carrier tracking ambiguity and its cause in signal tracking, and propose a receiver structure that can solve it. In order to prove the proposed receiver structure, we provide three signal tracking results. The first is the differential decoding result (secondary code sync) using the general GNSS receiver structure and the proposed receiver structure. The second is the IQ diagram before and after multiplying the secondary code demodulation when carrier tracking ambiguity is solved using the proposed receiver structure. The third is the carrier tracking result of the legacy GPS (L1 C/A) signal and the signal using TDPC.

• Journal of the Institute of Convergence Signal Processing
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• v.5 no.4
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• pp.325-332
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• 2004

In this paper, we propose a new DSSS-QPSK baseband modem receiver structure. A general receiver consists of matched filter, do-spreader, and DLL(Delay Locked Loop). In this paper, the matched filter plays a role of the do-spreader using the structure similarities between the matched filter and the de-spreader. As a result of the new receiver architecture, we can reduce the computational expenses and get the simpler receiver structure. This result can be used as an important part in designing the high speed modem. And, through the computer simulation and the experiment with the proposed architecture, we show that the proposed receiver structure yields fast operation speed and simple overall architecture.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.9A
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• pp.991-997
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• 2004

In this paper, we propose the architecture of modem receiver to fabricate HomePNA 2.0 chip. HomePNA suffers from inferior channel because of bridge tap, the effect of amateur HAM band and so on. To transfer data over such channel, HomePNA 2.0 uses training sequence to equalize channel and uses FD-QAM optionally as modulation method. So modem receiver demodulate QAM based signal and needs optimum architecture that fully uses these transmission feature. As a result of research, we define 2 mode function of modem receiver depending on TX/RX state. In this paper, particularly, we show the algorithm of equalizer, carrier phase recovery and frame synchromzationblock and propose architecture that improve the performance of channel equalization and is stable in operation. In the end, we estimate the performance of proposed HomePNA2.0 modem receiver over HomePNA TEST LOOP using SPW program.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.56 no.4
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• pp.784-789
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• 2007

This paper presents an implementation of a new type of architecture to improve an overflow problem on the network buffer. Each receiver channel of network system stores the message in its own buffer. If some receiver channel receives many messages, buffer overflow problem may occur for the channel. This paper proposes a network controller that implements a receiver channel with shared-memory to save all of the received messages from the every incomming channels. The proposed architecture is applied to ARINC-429, a real-time control network for commercial avionics system. For verifying performance of the architecture, ARINC-429 controller is designed using a SOPC platform, designed by Verilog and targeted to Xilinx Virtex-4 with a built-in PPC405 core.

• Proceedings of the KIEE Conference
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• 2003.11c
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• pp.894-897
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• 2003

Recently, the rapid growth of mobile radio system has led to an increasing demand of low-cost high performance communication IC's. In this paper, we have designed RF front end for wireless LAN receiver employ zero-IF architecture. A low-noise amplifier (LNA) and double-balanced mixer is included in a front end. The zero-IF architecture is easy to integrate and good for low power consumption, so that is coincided to requirement of wireless LAN. But the zero-IF architecture has a serious problem of large offset. Image-reject mixer is a good structure to solve offset problem. Using offset compensation circuit is good structure, too. The front end is implemented in 0.25 ${\mu}m$ CMOS technology. The front end has a noise figure of 5.6 dB, a power consumption of 16 mW and total gain of 22 dB.

• ETRI Journal
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• v.29 no.1
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• pp.79-88
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• 2007

This paper proposes a novel concept of adjusting the hardware size in a multi-carrier code division multiple access (MC-CDMA) receiver in real time as per the channel parameters such as delay spread, signal-to-noise ratio, transmission rate, and Doppler frequency. The fast Fourier transform (FFT) or inverse FFT (IFFT) size in orthogonal frequency division multiplexing (OFDM)/MC-CDMA transceivers varies from 1024 points to 16 points. Two low-power reconfigurable radix-4 256-point FFT processor architectures are proposed that can also be dynamically configured as 64-point and 16-point as per the channel parameters to prove the concept. By tailoring the clock of the higher FFT stages for longer FFTs and switching to shorter FFTs from longer FFTs, significant power saving is achieved. In addition, two 256 sub-carrier MC-CDMA receiver architectures are proposed which can also be configured for 64 sub-carriers in real time to prove the feasibility of the concept over the whole receiver.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.31A no.5
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• pp.10-17
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• 1994

Two protocols inclouding the receiver collision avoidance function are proposed for high-speed optical fiber LANs with finite users. The basic idea to avoid receiver collision is the grouping of destination nodes by the number of channels and it is accomplished in the architecture with or without one separate control channel. While the protocol with a control channel requires a tunable optical transmitter, a fixed optical transmitter and two fixed optical receiver, the other protocol requires a tunable optical transmitter and one fixed optical receiver. The performance of two receiver collision avoidance protocols is computed and analyzed under various system parameters. The numerical results show that the receiver collision avoidance protocol has better performance for a small load than the protocol without receiver collision avoidance.

• Proceedings of the Korean Institute of Navigation and Port Research Conference
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• v.2
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• pp.391-394
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• 2006

The paper deals with the experimental GNSS receiver built at the Czech Technical University for experiments with the real GNSS signal. The receiver is based on software defined radio architecture. Receiver consists of the RF front end and a digital processor based on programmable logic. Receiver RF front end supports GPS L1, L2, L5, WAAS/EGNOS, GALILEO L1, E5A, E5B signals as well as GLONASS L1 and L2 signals. The digital processor is based on Field Programmable Gate Array (FPGA) which supports embedded processor. The receiver is used for various experiments with the GNSS signals like GPS L1/EGNOS receiver, GLONASS receiver and investigation of the EGNOS signal availability for a land mobile user. On the base of experimental GNSS receiver the GPS L1, L2, EGNOS receiver for railway application was designed. The experimental receiver is also used in GNSS monitoring station, which is independent monitoring facility providing also raw monitoring data of the GPS, EGNOS and Galileo systems via internet.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.20 no.7
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• pp.657-663
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• 2009

A fully integrated single ended IR-UWB receiver is implemented using 0.18 ${\mu}m$ CMOS technology. The UWB receiver adopts the non-coherent architecture, which simplifies the RF architecture and reduces power consumption. The receiver consists of single-ended 2-stage LNAs, S2D, envelope detector, VGA, and comparator. The measured results show that sensitivity is -80.8 dBm at 1 Mbps and BER of $10^{-3}$. The receiver uses no external balun and the chip size is only $1.8{\times}0.9$ mm. The consumed current is very low with 13 mA at 1.8 V supply and the energy per bit performance is 23.4 nJ/bit.

• Proceedings of the Korea Electromagnetic Engineering Society Conference
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• 2000.11a
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• pp.154-157
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• 2000

One of the problems using DCR(Direct Conversion Receiver) type architecture are DC offset, Poor channel selectivity. APDP(Anti Parallel Diode Pair) can be mood candidate for the DCR frequency mixer due to its inherent 2nd harmonic suppression. APDP shows good IP2 and DC suppression. This paper describes single APDP LO power characteristics, IP2, and receiver structure utilizing APDP frequency mixer.